PCT: Create devicetree validation schema

This is the output of the automated scripts created to parse the dtb and dts files congruently Jira ESDP-27666 Change-Id: Ic82a3f813bcbe6e78ba5f9b68875293c5d4bc6d7 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3274878 Tested-by: Mark Mendez <mmendez@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2025-12-24 10:11:26 +03:00 · 2024-12-29 12:08:14 -08:00
parent c4d1462fd6
commit a2ee9f655f
172 changed files with 22145 additions and 0 deletions
--- a/Documentation/devicetree/bindings/firmware/tegra/nvidia,tegra194-safe-bpmp-hv.yaml
+++ b/Documentation/devicetree/bindings/firmware/tegra/nvidia,tegra194-safe-bpmp-hv.yaml
@@ -0,0 +1,104 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bpmp/nvidia,tegra194-safe-bpmp-hv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = nvidia,tegra194-safe-bpmp-hv is mentioned in the following drivers
+        - <TOP>/kernel/nvidia-oot/drivers/firmware/tegra/bpmp-tegra186-hv.c
+        - <TOP>/kernel/nvidia-oot/drivers/gpu/drm/tegra/virt.c
+
+     The following nodes use this compatibility
+        - /bpmp
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - nvidia,tegra194-safe-bpmp-hv
+
+  required:
+    - compatible
+
+properties:
+
+    mboxes:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        items:
+            minItems: 3
+            maxItems: 3
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x13
+                  maximum: 0x13
+
+    '#clock-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x1
+        maximum: 0x1
+
+    '#reset-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x1
+        maximum: 0x1
+
+    '#power-domain-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x1
+        maximum: 0x1
+
+    numa-node-id:
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x0
+        maximum: 0x0
+
+    ivc_queue:
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x0
+        maximum: 0xf
+
+    mempool:
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x3
+        maximum: 0x3
+
+required:
+    - compatible
+
+examples:
+    - |
+        bpmp {
+            compatible = "nvidia,tegra264-bpmp",
+                         "nvidia,tegra234-bpmp",
+                         "nvidia,tegra186-bpmp";
+            status = "disabled";
+            mboxes = <&top_hsp0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
+            memory-region = <&dram_cpu_bpmp_mail>;
+            #clock-cells = <1>;
+            #reset-cells = <1>;
+            #power-domain-cells = <1>;
+            numa-node-id = <0>;
+        };