PCT: Create devicetree validation schema

This is the output of the automated scripts created to parse the dtb and dts files congruently Jira ESDP-27666 Change-Id: Ic82a3f813bcbe6e78ba5f9b68875293c5d4bc6d7 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3274878 Tested-by: Mark Mendez <mmendez@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2025-12-24 10:11:26 +03:00 · 2024-12-29 12:08:14 -08:00
parent c4d1462fd6
commit a2ee9f655f
172 changed files with 22145 additions and 0 deletions
--- a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-aon.yaml
+++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-aon.yaml
@@ -0,0 +1,132 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio@cf00000/nvidia,tegra264-gpio-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = nvidia,tegra264-gpio-aon is mentioned in the following drivers
+        - <TOP>/kernel/kernel-oot/drivers/gpio/gpio-tegra186.c
+
+     The following nodes use this compatibility
+        - /bus@0/gpio@cf00000
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - nvidia,tegra264-gpio-aon
+
+  required:
+    - compatible
+
+properties:
+
+    reg-names:
+        $ref: "/schemas/types.yaml#/definitions/string-array"
+        items:
+            enum:
+                - security
+                - gpio
+
+
+    reg:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Registers are given by a tuple of two values:
+                - register address:
+                - register block size.
+        items:
+            minItems: 4
+            maxItems: 4
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0xcf00000
+                  maximum: 0xcf10000
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x1000
+                  maximum: 0x10000
+
+    interrupts:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Interrupts are give by a tuple of 3 values:
+                - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
+                  definitions in dt-bindings/interrupt-controller/arm-gic.h
+                - interrupt number
+                - trigger type (rising edge, falling edge, both, etc)
+                  definitions in dt-bindings/interrupt-controller/irq.h
+        items:
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x21a
+                  maximum: 0x21d
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x4
+                  maximum: 0x4
+
+    gpio-controller:
+        $ref: "/schemas/types.yaml#/definitions/flag"
+
+    '#gpio-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x2
+        maximum: 0x2
+
+    interrupt-controller:
+        $ref: "/schemas/types.yaml#/definitions/flag"
+
+    '#interrupt-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x2
+        maximum: 0x2
+
+required:
+    - compatible
+    - reg
+    - interrupts
+
+examples:
+    - |
+        gpio@cf00000 {
+            reg-names = "security, gpio";
+            compatible = "nvidia,tegra264-gpio-aon";
+            status = "disabled";
+            reg = <0x0 0x0cf00000 0x0 0x10000>,
+                  <0x0 0x0cf10000 0x0 0x1000>;
+            interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
+            gpio-controller;
+            #gpio-cells = <2>;
+            interrupt-controller;
+            #interrupt-cells = <2>;
+        };
--- a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-main.yaml
+++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-main.yaml
@@ -0,0 +1,160 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio@810c300000/nvidia,tegra264-gpio-main.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = nvidia,tegra264-gpio-main is mentioned in the following drivers
+        - <TOP>/kernel/kernel-oot/drivers/gpio/gpio-tegra186.c
+
+     The following nodes use this compatibility
+        - /bus@0/gpio@810c300000
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - nvidia,tegra264-gpio-main
+
+  required:
+    - compatible
+
+properties:
+
+    reg-names:
+        $ref: "/schemas/types.yaml#/definitions/string-array"
+        items:
+            enum:
+                - security
+                - gpio
+
+
+    reg:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Registers are given by a tuple of two values:
+                - register address:
+                - register block size.
+        items:
+            minItems: 4
+            maxItems: 4
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x81
+                  maximum: 0x81
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0xc300000
+                  maximum: 0xc310000
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x4000
+                  maximum: 0x4000
+
+    interrupts:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Interrupts are give by a tuple of 3 values:
+                - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
+                  definitions in dt-bindings/interrupt-controller/arm-gic.h
+                - interrupt number
+                - trigger type (rising edge, falling edge, both, etc)
+                  definitions in dt-bindings/interrupt-controller/irq.h
+        items:
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x5b
+                  maximum: 0x7a
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x4
+                  maximum: 0x4
+
+    gpio-controller:
+        $ref: "/schemas/types.yaml#/definitions/flag"
+
+    '#gpio-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x2
+        maximum: 0x2
+
+    interrupt-controller:
+        $ref: "/schemas/types.yaml#/definitions/flag"
+
+    '#interrupt-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x2
+        maximum: 0x2
+
+required:
+    - compatible
+    - reg
+    - interrupts
+
+examples:
+    - |
+        gpio@810c300000 {
+            reg-names = "security, gpio";
+            compatible = "nvidia,tegra264-gpio-main";
+            status = "disabled";
+            reg = <0x81 0x0c300000 0x0 0x4000>,
+                  <0x81 0x0c310000 0x0 0x4000>;
+            interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+            gpio-controller;
+            #gpio-cells = <2>;
+            interrupt-controller;
+            #interrupt-cells = <2>;
+        };
--- a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-uphy.yaml
+++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-uphy.yaml
@@ -0,0 +1,148 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio@a808300000/nvidia,tegra264-gpio-uphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = nvidia,tegra264-gpio-uphy is mentioned in the following drivers
+        - <TOP>/kernel/kernel-oot/drivers/gpio/gpio-tegra186.c
+
+     The following nodes use this compatibility
+        - /bus@0/gpio@a808300000
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - nvidia,tegra264-gpio-uphy
+
+  required:
+    - compatible
+
+properties:
+
+    reg-names:
+        $ref: "/schemas/types.yaml#/definitions/string-array"
+        items:
+            enum:
+                - security
+                - gpio
+
+
+    reg:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Registers are given by a tuple of two values:
+                - register address:
+                - register block size.
+        items:
+            minItems: 4
+            maxItems: 4
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0xa8
+                  maximum: 0xa8
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x8300000
+                  maximum: 0x8310000
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x2000
+                  maximum: 0x2000
+
+    interrupts:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Interrupts are give by a tuple of 3 values:
+                - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
+                  definitions in dt-bindings/interrupt-controller/arm-gic.h
+                - interrupt number
+                - trigger type (rising edge, falling edge, both, etc)
+                  definitions in dt-bindings/interrupt-controller/irq.h
+        items:
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x34b
+                  maximum: 0x35a
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x4
+                  maximum: 0x4
+
+    gpio-controller:
+        $ref: "/schemas/types.yaml#/definitions/flag"
+
+    '#gpio-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x2
+        maximum: 0x2
+
+    interrupt-controller:
+        $ref: "/schemas/types.yaml#/definitions/flag"
+
+    '#interrupt-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x2
+        maximum: 0x2
+
+    pinctrl-node:
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+
+required:
+    - compatible
+    - reg
+    - interrupts
+
+examples:
+    - |
+        gpio@a808300000 {
+            reg-names = "security, gpio";
+            compatible = "nvidia,tegra264-gpio-uphy";
+            status = "disabled";
+            reg = <0xa8 0x08300000 0x0 0x2000>,
+                  <0xa8 0x08310000 0x0 0x2000>;
+            interrupts = <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+            gpio-controller;
+            #gpio-cells = <2>;
+            interrupt-controller;
+            #interrupt-cells = <2>;
+            pinctrl-node = <&padctl_uphy>;
+        };
--- a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-main.yaml
+++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-main.yaml
@@ -0,0 +1,78 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinmux@810c281000/nvidia,tegra264-pinmux-main.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = nvidia,tegra264-pinmux-main is mentioned in the following drivers
+        - <TOP>/kernel/kernel-oot/drivers/gpio/gpio-tegra186.c
+        - <TOP>/kernel/kernel-oot/drivers/pinctrl/tegra/pinctrl-tegra264-generic.c
+        - <TOP>/kernel/kernel-oot/drivers/pinctrl/tegra/pinctrl-tegra264.c
+
+     The following nodes use this compatibility
+        - /bus@0/pinmux@810c281000
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - nvidia,tegra264-pinmux-main
+
+  required:
+    - compatible
+
+properties:
+
+    reg:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Registers are given by a tuple of two values:
+                - register address:
+                - register block size.
+        items:
+            minItems: 4
+            maxItems: 4
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x81
+                  maximum: 0x81
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0xc281000
+                  maximum: 0xc281000
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0xc000
+                  maximum: 0xc000
+
+required:
+    - compatible
+    - reg
+
+examples:
+    - |
+        pinmux@810c281000 {
+            compatible = "nvidia,tegra264-pinmux-main";
+            status = "disabled";
+            reg = <0x81 0x0c281000 0x0 0xc000>;
+        };
--- a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-uphy.yaml
+++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-uphy.yaml
@@ -0,0 +1,77 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinmux@a8082e0000/nvidia,tegra264-pinmux-uphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = nvidia,tegra264-pinmux-uphy is mentioned in the following drivers
+        - <TOP>/kernel/kernel-oot/drivers/gpio/gpio-tegra186.c
+        - <TOP>/kernel/kernel-oot/drivers/pinctrl/tegra/pinctrl-tegra264-generic.c
+
+     The following nodes use this compatibility
+        - /bus@0/pinmux@a8082e0000
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - nvidia,tegra264-pinmux-uphy
+
+  required:
+    - compatible
+
+properties:
+
+    reg:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Registers are given by a tuple of two values:
+                - register address:
+                - register block size.
+        items:
+            minItems: 4
+            maxItems: 4
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0xa8
+                  maximum: 0xa8
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x82e0000
+                  maximum: 0x82e0000
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x4000
+                  maximum: 0x4000
+
+required:
+    - compatible
+    - reg
+
+examples:
+    - |
+        pinmux@a8082e0000 {
+            compatible = "nvidia,tegra264-pinmux-uphy";
+            status = "disabled";
+            reg = <0xa8 0x082e0000 0x0 0x4000>;
+        };