PCT: Create devicetree validation schema

This is the output of the automated scripts created to parse the dtb and dts files congruently Jira ESDP-27666 Change-Id: Ic82a3f813bcbe6e78ba5f9b68875293c5d4bc6d7 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3274878 Tested-by: Mark Mendez <mmendez@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2025-12-23 17:55:05 +03:00 · 2024-12-29 12:08:14 -08:00
parent c4d1462fd6
commit a2ee9f655f
172 changed files with 22145 additions and 0 deletions
--- a/Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml
+++ b/Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml
@@ -0,0 +1,117 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pmu_tcu_smmu0@810a000000/arm,smmu-v3-pmcg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = arm,smmu-v3-pmcg is mentioned in the following drivers
+        - <TOP>/kernel/kernel-oot/drivers/perf/arm_smmuv3_pmu.c
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - arm,smmu-v3-pmcg
+
+  required:
+    - compatible
+
+properties:
+
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - arm,smmu-v3-pmcg
+
+    reg:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Registers are given by a tuple of two values:
+                - register address:
+                - register block size.
+        items:
+            minItems: 4
+            maxItems: 4
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x81
+                  maximum: 0x88
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x5002000
+                  maximum: 0xb1b3000
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x1000
+                  maximum: 0x1000
+
+    interrupts:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Interrupts are give by a tuple of 3 values:
+                - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
+                  definitions in dt-bindings/interrupt-controller/arm-gic.h
+                - interrupt number
+                - trigger type (rising edge, falling edge, both, etc)
+                  definitions in dt-bindings/interrupt-controller/irq.h
+        items:
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x6
+                  maximum: 0x341
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x1
+                  maximum: 0x1
+
+    ceid0-override:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        items:
+            minItems: 2
+            maxItems: 2
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x7
+                  maximum: 0x7
+
+required:
+    - compatible
+    - reg
+    - interrupts
+
+examples:
+    - |
+        pmu_tcu_smmu0@810a000000 {
+            compatible = "arm,smmu-v3-pmcg";
+            status = "disabled";
+            reg = <0x81 0x0a002000 0x0 0x1000>,
+                  <0x81 0x0a022000 0x0 0x1000>;
+            interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+        };
--- a/Documentation/devicetree/bindings/perf/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/perf/arm,smmu-v3.yaml
@@ -0,0 +1,132 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu@8105000000/arm,smmu-v3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = arm,smmu-v3 is mentioned in the following drivers
+        - <TOP>/kernel/kernel-oot/drivers/perf/arm_smmuv3_pmu.c
+        - <TOP>/kernel/kernel-oot/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+
+     The following nodes use this compatibility
+        - /bus@0/iommu@8105000000
+        - /bus@0/iommu@8106000000
+        - /bus@0/iommu@810a000000
+        - /bus@0/iommu@810b000000
+        - /bus@0/iommu@8806000000
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - arm,smmu-v3
+
+  required:
+    - compatible
+
+properties:
+
+    reg:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Registers are given by a tuple of two values:
+                - register address:
+                - register block size.
+        items:
+            minItems: 4
+            maxItems: 4
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x81
+                  maximum: 0x88
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x5000000
+                  maximum: 0xb000000
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x200000
+                  maximum: 0x200000
+
+    interrupts:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Interrupts are give by a tuple of 3 values:
+                - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
+                  definitions in dt-bindings/interrupt-controller/arm-gic.h
+                - interrupt number
+                - trigger type (rising edge, falling edge, both, etc)
+                  definitions in dt-bindings/interrupt-controller/irq.h
+        items:
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x1
+                  maximum: 0xe2
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x1
+                  maximum: 0x1
+
+    interrupt-names:
+        $ref: "/schemas/types.yaml#/definitions/string-array"
+        items:
+            enum:
+                - eventq
+                - gerror
+
+
+    dma-coherent:
+        $ref: "/schemas/types.yaml#/definitions/flag"
+
+    '#iommu-cells':
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x1
+        maximum: 0x1
+
+    numa-node-id:
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+        minimum: 0x0
+        maximum: 0x0
+
+required:
+    - compatible
+    - reg
+    - interrupts
+    - interrupt-names
+
+examples:
+    - |
+        iommu@8105000000 {
+            compatible = "arm,smmu-v3";
+            status = "disabled";
+            reg = <0x81 0x5000000 0x00 0x200000>;
+            interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
+            interrupt-names = "eventq",
+                              "gerror";
+            dma-coherent;
+            #iommu-cells = <1>;
+            numa-node-id = <0>;
+        };
--- a/Documentation/devicetree/bindings/perf/arm,statistical-profiling-extension-v1.yaml
+++ b/Documentation/devicetree/bindings/perf/arm,statistical-profiling-extension-v1.yaml
@@ -0,0 +1,74 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spe-pmu/arm,statistical-profiling-extension-v1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = arm,statistical-profiling-extension-v1 is mentioned in the following drivers
+        - <TOP>/kernel/kernel-oot/drivers/perf/arm_spe_pmu.c
+
+     The following nodes use this compatibility
+        - /spe-pmu
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - arm,statistical-profiling-extension-v1
+
+  required:
+    - compatible
+
+properties:
+
+    interrupts:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Interrupts are give by a tuple of 3 values:
+                - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
+                  definitions in dt-bindings/interrupt-controller/arm-gic.h
+                - interrupt number
+                - trigger type (rising edge, falling edge, both, etc)
+                  definitions in dt-bindings/interrupt-controller/irq.h
+        items:
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x1
+                  maximum: 0x1
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x5
+                  maximum: 0x5
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x8
+                  maximum: 0x8
+
+required:
+    - compatible
+    - interrupts
+
+examples:
+    - |
+        spe-pmu {
+            compatible = "arm,statistical-profiling-extension-v1";
+            interrupts = <GIC_PPI 5 8>;
+            status = "disabled";
+        };
--- a/Documentation/devicetree/bindings/perf/arm_cspmu/arm,coresight-pmu.yaml
+++ b/Documentation/devicetree/bindings/perf/arm_cspmu/arm,coresight-pmu.yaml
@@ -0,0 +1,120 @@
+# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ucf_uapmu@140c0000/arm,coresight-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FIXME -- add title
+
+maintainers:
+  - FIXME -- add maintainers
+
+description: |
+     the compatability = arm,coresight-pmu is mentioned in the following drivers
+        - <TOP>/kernel/kernel-oot/drivers/perf/arm_cspmu/arm_cspmu.c
+
+     The following nodes use this compatibility
+        - /ucf_uapmu@140c0000
+        - /disp_usb_apmu@8808900000
+        - /ucf_gpu_apmu@810c248000
+        - /uphy_apmu@a808880000
+        - /vision_apmu@818a000000
+
+select:
+  properties:
+    compatible:
+        minItems: 1
+        maxItems: 1
+        items:
+            enum:
+                - arm,coresight-pmu
+
+  required:
+    - compatible
+
+properties:
+
+    reg:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Registers are given by a tuple of two values:
+                - register address:
+                - register block size.
+        items:
+            minItems: 4
+            maxItems: 4
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0xa8
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x8880000
+                  maximum: 0x8a000000
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x1000
+                  maximum: 0x1000
+
+    cpus:
+        $ref: "/schemas/types.yaml#/definitions/uint32"
+
+    interrupts:
+        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
+        description: |
+            Interrupts are give by a tuple of 3 values:
+                - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
+                  definitions in dt-bindings/interrupt-controller/arm-gic.h
+                - interrupt number
+                - trigger type (rising edge, falling edge, both, etc)
+                  definitions in dt-bindings/interrupt-controller/irq.h
+        items:
+            items:
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x0
+                  maximum: 0x0
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x33
+                  maximum: 0x342
+                - $ref: "/schemas/types.yaml#/definitions/uint32"
+                  minimum: 0x4
+                  maximum: 0x4
+
+required:
+    - compatible
+    - reg
+    - interrupts
+
+examples:
+    - |
+        ucf_uapmu@140c0000 {
+            compatible = "arm,coresight-pmu";
+            status = "disabled";
+            reg = <0x0 0x140c0000 0x0 0x1000>;
+            cpus = <&cpu_0>,
+                   < &cpu_1>,
+                   < &cpu_2>,
+                   < &cpu_3>,
+                   <&cpu_4>,
+                   < &cpu_5>,
+                   < &cpu_6>,
+                   < &cpu_7>,
+                   <&cpu_8>,
+                   < &cpu_9>,
+                   < &cpu_10>,
+                   < &cpu_11>,
+                   <&cpu_12>,
+                   < &cpu_13>;
+            interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+        };