mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 17:25:35 +03:00
drivers: Remove unused headers
Remove all the unused headers. Bug 5054840 Change-Id: I4b441c6cb39025aa0c9d35c6f0f597ada5b1882b Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3349974 Reviewed-by: Brad Griffis <bgriffis@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Jon Hunter
@@ -1,249 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
||||||
/*
|
|
||||||
* Core private header for the pin control subsystem
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 ST-Ericsson SA
|
|
||||||
* Written on behalf of Linaro for ST-Ericsson
|
|
||||||
*
|
|
||||||
* Author: Linus Walleij <linus.walleij@linaro.org>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/kref.h>
|
|
||||||
#include <linux/mutex.h>
|
|
||||||
#include <linux/radix-tree.h>
|
|
||||||
#include <linux/pinctrl/pinconf.h>
|
|
||||||
#include <linux/pinctrl/machine.h>
|
|
||||||
|
|
||||||
struct pinctrl_gpio_range;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct pinctrl_dev - pin control class device
|
|
||||||
* @node: node to include this pin controller in the global pin controller list
|
|
||||||
* @desc: the pin controller descriptor supplied when initializing this pin
|
|
||||||
* controller
|
|
||||||
* @pin_desc_tree: each pin descriptor for this pin controller is stored in
|
|
||||||
* this radix tree
|
|
||||||
* @pin_group_tree: optionally each pin group can be stored in this radix tree
|
|
||||||
* @num_groups: optionally number of groups can be kept here
|
|
||||||
* @pin_function_tree: optionally each function can be stored in this radix tree
|
|
||||||
* @num_functions: optionally number of functions can be kept here
|
|
||||||
* @gpio_ranges: a list of GPIO ranges that is handled by this pin controller,
|
|
||||||
* ranges are added to this list at runtime
|
|
||||||
* @dev: the device entry for this pin controller
|
|
||||||
* @owner: module providing the pin controller, used for refcounting
|
|
||||||
* @driver_data: driver data for drivers registering to the pin controller
|
|
||||||
* subsystem
|
|
||||||
* @p: result of pinctrl_get() for this device
|
|
||||||
* @hog_default: default state for pins hogged by this device
|
|
||||||
* @hog_sleep: sleep state for pins hogged by this device
|
|
||||||
* @mutex: mutex taken on each pin controller specific action
|
|
||||||
* @device_root: debugfs root for this device
|
|
||||||
*/
|
|
||||||
struct pinctrl_dev {
|
|
||||||
struct list_head node;
|
|
||||||
struct pinctrl_desc *desc;
|
|
||||||
struct radix_tree_root pin_desc_tree;
|
|
||||||
#ifdef CONFIG_GENERIC_PINCTRL_GROUPS
|
|
||||||
struct radix_tree_root pin_group_tree;
|
|
||||||
unsigned int num_groups;
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS
|
|
||||||
struct radix_tree_root pin_function_tree;
|
|
||||||
unsigned int num_functions;
|
|
||||||
#endif
|
|
||||||
struct list_head gpio_ranges;
|
|
||||||
struct device *dev;
|
|
||||||
struct module *owner;
|
|
||||||
void *driver_data;
|
|
||||||
struct pinctrl *p;
|
|
||||||
struct pinctrl_state *hog_default;
|
|
||||||
struct pinctrl_state *hog_sleep;
|
|
||||||
struct mutex mutex;
|
|
||||||
#ifdef CONFIG_DEBUG_FS
|
|
||||||
struct dentry *device_root;
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct pinctrl - per-device pin control state holder
|
|
||||||
* @node: global list node
|
|
||||||
* @dev: the device using this pin control handle
|
|
||||||
* @states: a list of states for this device
|
|
||||||
* @state: the current state
|
|
||||||
* @dt_maps: the mapping table chunks dynamically parsed from device tree for
|
|
||||||
* this device, if any
|
|
||||||
* @users: reference count
|
|
||||||
*/
|
|
||||||
struct pinctrl {
|
|
||||||
struct list_head node;
|
|
||||||
struct device *dev;
|
|
||||||
struct list_head states;
|
|
||||||
struct pinctrl_state *state;
|
|
||||||
struct list_head dt_maps;
|
|
||||||
struct kref users;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct pinctrl_state - a pinctrl state for a device
|
|
||||||
* @node: list node for struct pinctrl's @states field
|
|
||||||
* @name: the name of this state
|
|
||||||
* @settings: a list of settings for this state
|
|
||||||
*/
|
|
||||||
struct pinctrl_state {
|
|
||||||
struct list_head node;
|
|
||||||
const char *name;
|
|
||||||
struct list_head settings;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct pinctrl_setting_mux - setting data for MAP_TYPE_MUX_GROUP
|
|
||||||
* @group: the group selector to program
|
|
||||||
* @func: the function selector to program
|
|
||||||
*/
|
|
||||||
struct pinctrl_setting_mux {
|
|
||||||
unsigned group;
|
|
||||||
unsigned func;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct pinctrl_setting_configs - setting data for MAP_TYPE_CONFIGS_*
|
|
||||||
* @group_or_pin: the group selector or pin ID to program
|
|
||||||
* @configs: a pointer to an array of config parameters/values to program into
|
|
||||||
* hardware. Each individual pin controller defines the format and meaning
|
|
||||||
* of config parameters.
|
|
||||||
* @num_configs: the number of entries in array @configs
|
|
||||||
*/
|
|
||||||
struct pinctrl_setting_configs {
|
|
||||||
unsigned group_or_pin;
|
|
||||||
unsigned long *configs;
|
|
||||||
unsigned num_configs;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct pinctrl_setting - an individual mux or config setting
|
|
||||||
* @node: list node for struct pinctrl_settings's @settings field
|
|
||||||
* @type: the type of setting
|
|
||||||
* @pctldev: pin control device handling to be programmed. Not used for
|
|
||||||
* PIN_MAP_TYPE_DUMMY_STATE.
|
|
||||||
* @dev_name: the name of the device using this state
|
|
||||||
* @data: Data specific to the setting type
|
|
||||||
*/
|
|
||||||
struct pinctrl_setting {
|
|
||||||
struct list_head node;
|
|
||||||
enum pinctrl_map_type type;
|
|
||||||
struct pinctrl_dev *pctldev;
|
|
||||||
const char *dev_name;
|
|
||||||
union {
|
|
||||||
struct pinctrl_setting_mux mux;
|
|
||||||
struct pinctrl_setting_configs configs;
|
|
||||||
} data;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct pin_desc - pin descriptor for each physical pin in the arch
|
|
||||||
* @pctldev: corresponding pin control device
|
|
||||||
* @name: a name for the pin, e.g. the name of the pin/pad/finger on a
|
|
||||||
* datasheet or such
|
|
||||||
* @dynamic_name: if the name of this pin was dynamically allocated
|
|
||||||
* @drv_data: driver-defined per-pin data. pinctrl core does not touch this
|
|
||||||
* @mux_usecount: If zero, the pin is not claimed, and @owner should be NULL.
|
|
||||||
* If non-zero, this pin is claimed by @owner. This field is an integer
|
|
||||||
* rather than a boolean, since pinctrl_get() might process multiple
|
|
||||||
* mapping table entries that refer to, and hence claim, the same group
|
|
||||||
* or pin, and each of these will increment the @usecount.
|
|
||||||
* @mux_owner: The name of device that called pinctrl_get().
|
|
||||||
* @mux_setting: The most recent selected mux setting for this pin, if any.
|
|
||||||
* @gpio_owner: If pinctrl_gpio_request() was called for this pin, this is
|
|
||||||
* the name of the GPIO that "owns" this pin.
|
|
||||||
*/
|
|
||||||
struct pin_desc {
|
|
||||||
struct pinctrl_dev *pctldev;
|
|
||||||
const char *name;
|
|
||||||
bool dynamic_name;
|
|
||||||
void *drv_data;
|
|
||||||
/* These fields only added when supporting pinmux drivers */
|
|
||||||
#ifdef CONFIG_PINMUX
|
|
||||||
unsigned mux_usecount;
|
|
||||||
const char *mux_owner;
|
|
||||||
const struct pinctrl_setting_mux *mux_setting;
|
|
||||||
const char *gpio_owner;
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct pinctrl_maps - a list item containing part of the mapping table
|
|
||||||
* @node: mapping table list node
|
|
||||||
* @maps: array of mapping table entries
|
|
||||||
* @num_maps: the number of entries in @maps
|
|
||||||
*/
|
|
||||||
struct pinctrl_maps {
|
|
||||||
struct list_head node;
|
|
||||||
const struct pinctrl_map *maps;
|
|
||||||
unsigned num_maps;
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef CONFIG_GENERIC_PINCTRL_GROUPS
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct group_desc - generic pin group descriptor
|
|
||||||
* @name: name of the pin group
|
|
||||||
* @pins: array of pins that belong to the group
|
|
||||||
* @num_pins: number of pins in the group
|
|
||||||
* @data: pin controller driver specific data
|
|
||||||
*/
|
|
||||||
struct group_desc {
|
|
||||||
const char *name;
|
|
||||||
int *pins;
|
|
||||||
int num_pins;
|
|
||||||
void *data;
|
|
||||||
};
|
|
||||||
|
|
||||||
int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev);
|
|
||||||
|
|
||||||
const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev,
|
|
||||||
unsigned int group_selector);
|
|
||||||
|
|
||||||
int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev,
|
|
||||||
unsigned int group_selector,
|
|
||||||
const unsigned int **pins,
|
|
||||||
unsigned int *npins);
|
|
||||||
|
|
||||||
struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev,
|
|
||||||
unsigned int group_selector);
|
|
||||||
|
|
||||||
int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
|
|
||||||
int *gpins, int ngpins, void *data);
|
|
||||||
|
|
||||||
int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev,
|
|
||||||
unsigned int group_selector);
|
|
||||||
|
|
||||||
#endif /* CONFIG_GENERIC_PINCTRL_GROUPS */
|
|
||||||
|
|
||||||
struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
|
|
||||||
struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np);
|
|
||||||
int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
|
|
||||||
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
|
|
||||||
int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
|
|
||||||
const char *pin_group);
|
|
||||||
|
|
||||||
static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
|
|
||||||
unsigned int pin)
|
|
||||||
{
|
|
||||||
return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
|
|
||||||
}
|
|
||||||
|
|
||||||
extern struct pinctrl_gpio_range *
|
|
||||||
pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
|
|
||||||
unsigned int pin);
|
|
||||||
|
|
||||||
extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
|
|
||||||
extern int pinctrl_force_default(struct pinctrl_dev *pctldev);
|
|
||||||
|
|
||||||
extern struct mutex pinctrl_maps_mutex;
|
|
||||||
extern struct list_head pinctrl_maps;
|
|
||||||
|
|
||||||
#define for_each_maps(_maps_node_, _i_, _map_) \
|
|
||||||
list_for_each_entry(_maps_node_, &pinctrl_maps, node) \
|
|
||||||
for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \
|
|
||||||
_i_ < _maps_node_->num_maps; \
|
|
||||||
_i_++, _map_ = &_maps_node_->maps[_i_])
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,407 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0 */
|
|
||||||
/*
|
|
||||||
* sgtl5000.h - SGTL5000 audio codec interface
|
|
||||||
*
|
|
||||||
* Copyright 2010-2011 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _SGTL5000_H
|
|
||||||
#define _SGTL5000_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Registers addresses
|
|
||||||
*/
|
|
||||||
#define SGTL5000_CHIP_ID 0x0000
|
|
||||||
#define SGTL5000_CHIP_DIG_POWER 0x0002
|
|
||||||
#define SGTL5000_CHIP_CLK_CTRL 0x0004
|
|
||||||
#define SGTL5000_CHIP_I2S_CTRL 0x0006
|
|
||||||
#define SGTL5000_CHIP_SSS_CTRL 0x000a
|
|
||||||
#define SGTL5000_CHIP_ADCDAC_CTRL 0x000e
|
|
||||||
#define SGTL5000_CHIP_DAC_VOL 0x0010
|
|
||||||
#define SGTL5000_CHIP_PAD_STRENGTH 0x0014
|
|
||||||
#define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020
|
|
||||||
#define SGTL5000_CHIP_ANA_HP_CTRL 0x0022
|
|
||||||
#define SGTL5000_CHIP_ANA_CTRL 0x0024
|
|
||||||
#define SGTL5000_CHIP_LINREG_CTRL 0x0026
|
|
||||||
#define SGTL5000_CHIP_REF_CTRL 0x0028
|
|
||||||
#define SGTL5000_CHIP_MIC_CTRL 0x002a
|
|
||||||
#define SGTL5000_CHIP_LINE_OUT_CTRL 0x002c
|
|
||||||
#define SGTL5000_CHIP_LINE_OUT_VOL 0x002e
|
|
||||||
#define SGTL5000_CHIP_ANA_POWER 0x0030
|
|
||||||
#define SGTL5000_CHIP_PLL_CTRL 0x0032
|
|
||||||
#define SGTL5000_CHIP_CLK_TOP_CTRL 0x0034
|
|
||||||
#define SGTL5000_CHIP_ANA_STATUS 0x0036
|
|
||||||
#define SGTL5000_CHIP_SHORT_CTRL 0x003c
|
|
||||||
#define SGTL5000_CHIP_ANA_TEST2 0x003a
|
|
||||||
#define SGTL5000_DAP_CTRL 0x0100
|
|
||||||
#define SGTL5000_DAP_PEQ 0x0102
|
|
||||||
#define SGTL5000_DAP_BASS_ENHANCE 0x0104
|
|
||||||
#define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106
|
|
||||||
#define SGTL5000_DAP_AUDIO_EQ 0x0108
|
|
||||||
#define SGTL5000_DAP_SURROUND 0x010a
|
|
||||||
#define SGTL5000_DAP_FLT_COEF_ACCESS 0x010c
|
|
||||||
#define SGTL5000_DAP_COEF_WR_B0_MSB 0x010e
|
|
||||||
#define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110
|
|
||||||
#define SGTL5000_DAP_EQ_BASS_BAND0 0x0116
|
|
||||||
#define SGTL5000_DAP_EQ_BASS_BAND1 0x0118
|
|
||||||
#define SGTL5000_DAP_EQ_BASS_BAND2 0x011a
|
|
||||||
#define SGTL5000_DAP_EQ_BASS_BAND3 0x011c
|
|
||||||
#define SGTL5000_DAP_EQ_BASS_BAND4 0x011e
|
|
||||||
#define SGTL5000_DAP_MAIN_CHAN 0x0120
|
|
||||||
#define SGTL5000_DAP_MIX_CHAN 0x0122
|
|
||||||
#define SGTL5000_DAP_AVC_CTRL 0x0124
|
|
||||||
#define SGTL5000_DAP_AVC_THRESHOLD 0x0126
|
|
||||||
#define SGTL5000_DAP_AVC_ATTACK 0x0128
|
|
||||||
#define SGTL5000_DAP_AVC_DECAY 0x012a
|
|
||||||
#define SGTL5000_DAP_COEF_WR_B1_MSB 0x012c
|
|
||||||
#define SGTL5000_DAP_COEF_WR_B1_LSB 0x012e
|
|
||||||
#define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130
|
|
||||||
#define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132
|
|
||||||
#define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134
|
|
||||||
#define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136
|
|
||||||
#define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138
|
|
||||||
#define SGTL5000_DAP_COEF_WR_A2_LSB 0x013a
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Field Definitions.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_ID
|
|
||||||
*/
|
|
||||||
#define SGTL5000_PARTID_MASK 0xff00
|
|
||||||
#define SGTL5000_PARTID_SHIFT 8
|
|
||||||
#define SGTL5000_PARTID_WIDTH 8
|
|
||||||
#define SGTL5000_PARTID_PART_ID 0xa0
|
|
||||||
#define SGTL5000_REVID_MASK 0x00ff
|
|
||||||
#define SGTL5000_REVID_SHIFT 0
|
|
||||||
#define SGTL5000_REVID_WIDTH 8
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_DIG_POWER
|
|
||||||
*/
|
|
||||||
#define SGTL5000_ADC_EN 0x0040
|
|
||||||
#define SGTL5000_DAC_EN 0x0020
|
|
||||||
#define SGTL5000_DAP_POWERUP 0x0010
|
|
||||||
#define SGTL5000_I2S_OUT_POWERUP 0x0002
|
|
||||||
#define SGTL5000_I2S_IN_POWERUP 0x0001
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_CLK_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_CHIP_CLK_CTRL_DEFAULT 0x0008
|
|
||||||
#define SGTL5000_RATE_MODE_MASK 0x0030
|
|
||||||
#define SGTL5000_RATE_MODE_SHIFT 4
|
|
||||||
#define SGTL5000_RATE_MODE_WIDTH 2
|
|
||||||
#define SGTL5000_RATE_MODE_DIV_1 0
|
|
||||||
#define SGTL5000_RATE_MODE_DIV_2 1
|
|
||||||
#define SGTL5000_RATE_MODE_DIV_4 2
|
|
||||||
#define SGTL5000_RATE_MODE_DIV_6 3
|
|
||||||
#define SGTL5000_SYS_FS_MASK 0x000c
|
|
||||||
#define SGTL5000_SYS_FS_SHIFT 2
|
|
||||||
#define SGTL5000_SYS_FS_WIDTH 2
|
|
||||||
#define SGTL5000_SYS_FS_32k 0x0
|
|
||||||
#define SGTL5000_SYS_FS_44_1k 0x1
|
|
||||||
#define SGTL5000_SYS_FS_48k 0x2
|
|
||||||
#define SGTL5000_SYS_FS_96k 0x3
|
|
||||||
#define SGTL5000_MCLK_FREQ_MASK 0x0003
|
|
||||||
#define SGTL5000_MCLK_FREQ_SHIFT 0
|
|
||||||
#define SGTL5000_MCLK_FREQ_WIDTH 2
|
|
||||||
#define SGTL5000_MCLK_FREQ_256FS 0x0
|
|
||||||
#define SGTL5000_MCLK_FREQ_384FS 0x1
|
|
||||||
#define SGTL5000_MCLK_FREQ_512FS 0x2
|
|
||||||
#define SGTL5000_MCLK_FREQ_PLL 0x3
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_I2S_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_I2S_SCLKFREQ_MASK 0x0100
|
|
||||||
#define SGTL5000_I2S_SCLKFREQ_SHIFT 8
|
|
||||||
#define SGTL5000_I2S_SCLKFREQ_WIDTH 1
|
|
||||||
#define SGTL5000_I2S_SCLKFREQ_64FS 0x0
|
|
||||||
#define SGTL5000_I2S_SCLKFREQ_32FS 0x1 /* Not for RJ mode */
|
|
||||||
#define SGTL5000_I2S_MASTER 0x0080
|
|
||||||
#define SGTL5000_I2S_SCLK_INV 0x0040
|
|
||||||
#define SGTL5000_I2S_DLEN_MASK 0x0030
|
|
||||||
#define SGTL5000_I2S_DLEN_SHIFT 4
|
|
||||||
#define SGTL5000_I2S_DLEN_WIDTH 2
|
|
||||||
#define SGTL5000_I2S_DLEN_32 0x0
|
|
||||||
#define SGTL5000_I2S_DLEN_24 0x1
|
|
||||||
#define SGTL5000_I2S_DLEN_20 0x2
|
|
||||||
#define SGTL5000_I2S_DLEN_16 0x3
|
|
||||||
#define SGTL5000_I2S_MODE_MASK 0x000c
|
|
||||||
#define SGTL5000_I2S_MODE_SHIFT 2
|
|
||||||
#define SGTL5000_I2S_MODE_WIDTH 2
|
|
||||||
#define SGTL5000_I2S_MODE_I2S_LJ 0x0
|
|
||||||
#define SGTL5000_I2S_MODE_RJ 0x1
|
|
||||||
#define SGTL5000_I2S_MODE_PCM 0x2
|
|
||||||
#define SGTL5000_I2S_LRALIGN 0x0002
|
|
||||||
#define SGTL5000_I2S_LRPOL 0x0001 /* set for which mode */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_SSS_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_DAP_MIX_LRSWAP 0x4000
|
|
||||||
#define SGTL5000_DAP_LRSWAP 0x2000
|
|
||||||
#define SGTL5000_DAC_LRSWAP 0x1000
|
|
||||||
#define SGTL5000_I2S_OUT_LRSWAP 0x0400
|
|
||||||
#define SGTL5000_DAP_MIX_SEL_MASK 0x0300
|
|
||||||
#define SGTL5000_DAP_MIX_SEL_SHIFT 8
|
|
||||||
#define SGTL5000_DAP_MIX_SEL_WIDTH 2
|
|
||||||
#define SGTL5000_DAP_MIX_SEL_ADC 0x0
|
|
||||||
#define SGTL5000_DAP_MIX_SEL_I2S_IN 0x1
|
|
||||||
#define SGTL5000_DAP_SEL_MASK 0x00c0
|
|
||||||
#define SGTL5000_DAP_SEL_SHIFT 6
|
|
||||||
#define SGTL5000_DAP_SEL_WIDTH 2
|
|
||||||
#define SGTL5000_DAP_SEL_ADC 0x0
|
|
||||||
#define SGTL5000_DAP_SEL_I2S_IN 0x1
|
|
||||||
#define SGTL5000_DAC_SEL_MASK 0x0030
|
|
||||||
#define SGTL5000_DAC_SEL_SHIFT 4
|
|
||||||
#define SGTL5000_DAC_SEL_WIDTH 2
|
|
||||||
#define SGTL5000_DAC_SEL_ADC 0x0
|
|
||||||
#define SGTL5000_DAC_SEL_I2S_IN 0x1
|
|
||||||
#define SGTL5000_DAC_SEL_DAP 0x3
|
|
||||||
#define SGTL5000_I2S_OUT_SEL_MASK 0x0003
|
|
||||||
#define SGTL5000_I2S_OUT_SEL_SHIFT 0
|
|
||||||
#define SGTL5000_I2S_OUT_SEL_WIDTH 2
|
|
||||||
#define SGTL5000_I2S_OUT_SEL_ADC 0x0
|
|
||||||
#define SGTL5000_I2S_OUT_SEL_I2S_IN 0x1
|
|
||||||
#define SGTL5000_I2S_OUT_SEL_DAP 0x3
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_ADCDAC_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000
|
|
||||||
#define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000
|
|
||||||
#define SGTL5000_DAC_VOL_RAMP_EN 0x0200
|
|
||||||
#define SGTL5000_DAC_VOL_RAMP_EXPO 0x0100
|
|
||||||
#define SGTL5000_DAC_MUTE_RIGHT 0x0008
|
|
||||||
#define SGTL5000_DAC_MUTE_LEFT 0x0004
|
|
||||||
#define SGTL5000_ADC_HPF_FREEZE 0x0002
|
|
||||||
#define SGTL5000_ADC_HPF_BYPASS 0x0001
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_DAC_VOL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_DAC_VOL_RIGHT_MASK 0xff00
|
|
||||||
#define SGTL5000_DAC_VOL_RIGHT_SHIFT 8
|
|
||||||
#define SGTL5000_DAC_VOL_RIGHT_WIDTH 8
|
|
||||||
#define SGTL5000_DAC_VOL_LEFT_MASK 0x00ff
|
|
||||||
#define SGTL5000_DAC_VOL_LEFT_SHIFT 0
|
|
||||||
#define SGTL5000_DAC_VOL_LEFT_WIDTH 8
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_PAD_STRENGTH
|
|
||||||
*/
|
|
||||||
#define SGTL5000_PAD_I2S_LRCLK_MASK 0x0300
|
|
||||||
#define SGTL5000_PAD_I2S_LRCLK_SHIFT 8
|
|
||||||
#define SGTL5000_PAD_I2S_LRCLK_WIDTH 2
|
|
||||||
#define SGTL5000_PAD_I2S_SCLK_MASK 0x00c0
|
|
||||||
#define SGTL5000_PAD_I2S_SCLK_SHIFT 6
|
|
||||||
#define SGTL5000_PAD_I2S_SCLK_WIDTH 2
|
|
||||||
#define SGTL5000_PAD_I2S_DOUT_MASK 0x0030
|
|
||||||
#define SGTL5000_PAD_I2S_DOUT_SHIFT 4
|
|
||||||
#define SGTL5000_PAD_I2S_DOUT_WIDTH 2
|
|
||||||
#define SGTL5000_PAD_I2C_SDA_MASK 0x000c
|
|
||||||
#define SGTL5000_PAD_I2C_SDA_SHIFT 2
|
|
||||||
#define SGTL5000_PAD_I2C_SDA_WIDTH 2
|
|
||||||
#define SGTL5000_PAD_I2C_SCL_MASK 0x0003
|
|
||||||
#define SGTL5000_PAD_I2C_SCL_SHIFT 0
|
|
||||||
#define SGTL5000_PAD_I2C_SCL_WIDTH 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_ANA_ADC_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_ADC_VOL_M6DB 0x0100
|
|
||||||
#define SGTL5000_ADC_VOL_RIGHT_MASK 0x00f0
|
|
||||||
#define SGTL5000_ADC_VOL_RIGHT_SHIFT 4
|
|
||||||
#define SGTL5000_ADC_VOL_RIGHT_WIDTH 4
|
|
||||||
#define SGTL5000_ADC_VOL_LEFT_MASK 0x000f
|
|
||||||
#define SGTL5000_ADC_VOL_LEFT_SHIFT 0
|
|
||||||
#define SGTL5000_ADC_VOL_LEFT_WIDTH 4
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_ANA_HP_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_HP_VOL_RIGHT_MASK 0x7f00
|
|
||||||
#define SGTL5000_HP_VOL_RIGHT_SHIFT 8
|
|
||||||
#define SGTL5000_HP_VOL_RIGHT_WIDTH 7
|
|
||||||
#define SGTL5000_HP_VOL_LEFT_MASK 0x007f
|
|
||||||
#define SGTL5000_HP_VOL_LEFT_SHIFT 0
|
|
||||||
#define SGTL5000_HP_VOL_LEFT_WIDTH 7
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_ANA_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_CHIP_ANA_CTRL_DEFAULT 0x0133
|
|
||||||
#define SGTL5000_LINE_OUT_MUTE 0x0100
|
|
||||||
#define SGTL5000_HP_SEL_MASK 0x0040
|
|
||||||
#define SGTL5000_HP_SEL_SHIFT 6
|
|
||||||
#define SGTL5000_HP_SEL_WIDTH 1
|
|
||||||
#define SGTL5000_HP_SEL_DAC 0x0
|
|
||||||
#define SGTL5000_HP_SEL_LINE_IN 0x1
|
|
||||||
#define SGTL5000_HP_ZCD_EN 0x0020
|
|
||||||
#define SGTL5000_HP_MUTE 0x0010
|
|
||||||
#define SGTL5000_ADC_SEL_MASK 0x0004
|
|
||||||
#define SGTL5000_ADC_SEL_SHIFT 2
|
|
||||||
#define SGTL5000_ADC_SEL_WIDTH 1
|
|
||||||
#define SGTL5000_ADC_SEL_MIC 0x0
|
|
||||||
#define SGTL5000_ADC_SEL_LINE_IN 0x1
|
|
||||||
#define SGTL5000_ADC_ZCD_EN 0x0002
|
|
||||||
#define SGTL5000_ADC_MUTE 0x0001
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_LINREG_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_VDDC_MAN_ASSN_MASK 0x0040
|
|
||||||
#define SGTL5000_VDDC_MAN_ASSN_SHIFT 6
|
|
||||||
#define SGTL5000_VDDC_MAN_ASSN_WIDTH 1
|
|
||||||
#define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0
|
|
||||||
#define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x1
|
|
||||||
#define SGTL5000_VDDC_ASSN_OVRD 0x0020
|
|
||||||
#define SGTL5000_LINREG_VDDD_MASK 0x000f
|
|
||||||
#define SGTL5000_LINREG_VDDD_SHIFT 0
|
|
||||||
#define SGTL5000_LINREG_VDDD_WIDTH 4
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_REF_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_ANA_GND_MASK 0x01f0
|
|
||||||
#define SGTL5000_ANA_GND_SHIFT 4
|
|
||||||
#define SGTL5000_ANA_GND_WIDTH 5
|
|
||||||
#define SGTL5000_ANA_GND_BASE 800 /* mv */
|
|
||||||
#define SGTL5000_ANA_GND_STP 25 /*mv */
|
|
||||||
#define SGTL5000_BIAS_CTRL_MASK 0x000e
|
|
||||||
#define SGTL5000_BIAS_CTRL_SHIFT 1
|
|
||||||
#define SGTL5000_BIAS_CTRL_WIDTH 3
|
|
||||||
#define SGTL5000_SMALL_POP 0x0001
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_MIC_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_BIAS_R_MASK 0x0300
|
|
||||||
#define SGTL5000_BIAS_R_SHIFT 8
|
|
||||||
#define SGTL5000_BIAS_R_WIDTH 2
|
|
||||||
#define SGTL5000_BIAS_R_off 0x0
|
|
||||||
#define SGTL5000_BIAS_R_2K 0x1
|
|
||||||
#define SGTL5000_BIAS_R_4k 0x2
|
|
||||||
#define SGTL5000_BIAS_R_8k 0x3
|
|
||||||
#define SGTL5000_BIAS_VOLT_MASK 0x0070
|
|
||||||
#define SGTL5000_BIAS_VOLT_SHIFT 4
|
|
||||||
#define SGTL5000_BIAS_VOLT_WIDTH 3
|
|
||||||
#define SGTL5000_MIC_GAIN_MASK 0x0003
|
|
||||||
#define SGTL5000_MIC_GAIN_SHIFT 0
|
|
||||||
#define SGTL5000_MIC_GAIN_WIDTH 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_LINE_OUT_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_LINE_OUT_CURRENT_MASK 0x0f00
|
|
||||||
#define SGTL5000_LINE_OUT_CURRENT_SHIFT 8
|
|
||||||
#define SGTL5000_LINE_OUT_CURRENT_WIDTH 4
|
|
||||||
#define SGTL5000_LINE_OUT_CURRENT_180u 0x0
|
|
||||||
#define SGTL5000_LINE_OUT_CURRENT_270u 0x1
|
|
||||||
#define SGTL5000_LINE_OUT_CURRENT_360u 0x3
|
|
||||||
#define SGTL5000_LINE_OUT_CURRENT_450u 0x7
|
|
||||||
#define SGTL5000_LINE_OUT_CURRENT_540u 0xf
|
|
||||||
#define SGTL5000_LINE_OUT_GND_MASK 0x003f
|
|
||||||
#define SGTL5000_LINE_OUT_GND_SHIFT 0
|
|
||||||
#define SGTL5000_LINE_OUT_GND_WIDTH 6
|
|
||||||
#define SGTL5000_LINE_OUT_GND_BASE 800 /* mv */
|
|
||||||
#define SGTL5000_LINE_OUT_GND_STP 25
|
|
||||||
#define SGTL5000_LINE_OUT_GND_MAX 0x23
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_LINE_OUT_VOL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_LINE_OUT_VOL_RIGHT_MASK 0x1f00
|
|
||||||
#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 8
|
|
||||||
#define SGTL5000_LINE_OUT_VOL_RIGHT_WIDTH 5
|
|
||||||
#define SGTL5000_LINE_OUT_VOL_LEFT_MASK 0x001f
|
|
||||||
#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0
|
|
||||||
#define SGTL5000_LINE_OUT_VOL_LEFT_WIDTH 5
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_ANA_POWER
|
|
||||||
*/
|
|
||||||
#define SGTL5000_ANA_POWER_DEFAULT 0x7060
|
|
||||||
#define SGTL5000_DAC_STEREO 0x4000
|
|
||||||
#define SGTL5000_LINREG_SIMPLE_POWERUP 0x2000
|
|
||||||
#define SGTL5000_STARTUP_POWERUP 0x1000
|
|
||||||
#define SGTL5000_VDDC_CHRGPMP_POWERUP 0x0800
|
|
||||||
#define SGTL5000_PLL_POWERUP 0x0400
|
|
||||||
#define SGTL5000_LINEREG_D_POWERUP 0x0200
|
|
||||||
#define SGTL5000_VCOAMP_POWERUP 0x0100
|
|
||||||
#define SGTL5000_VAG_POWERUP 0x0080
|
|
||||||
#define SGTL5000_ADC_STEREO 0x0040
|
|
||||||
#define SGTL5000_REFTOP_POWERUP 0x0020
|
|
||||||
#define SGTL5000_HP_POWERUP 0x0010
|
|
||||||
#define SGTL5000_DAC_POWERUP 0x0008
|
|
||||||
#define SGTL5000_CAPLESS_HP_POWERUP 0x0004
|
|
||||||
#define SGTL5000_ADC_POWERUP 0x0002
|
|
||||||
#define SGTL5000_LINE_OUT_POWERUP 0x0001
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_PLL_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_PLL_INT_DIV_MASK 0xf800
|
|
||||||
#define SGTL5000_PLL_INT_DIV_SHIFT 11
|
|
||||||
#define SGTL5000_PLL_INT_DIV_WIDTH 5
|
|
||||||
#define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff
|
|
||||||
#define SGTL5000_PLL_FRAC_DIV_SHIFT 0
|
|
||||||
#define SGTL5000_PLL_FRAC_DIV_WIDTH 11
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_CLK_TOP_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_INT_OSC_EN 0x0800
|
|
||||||
#define SGTL5000_INPUT_FREQ_DIV2 0x0008
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_ANA_STATUS
|
|
||||||
*/
|
|
||||||
#define SGTL5000_HP_LRSHORT 0x0200
|
|
||||||
#define SGTL5000_CAPLESS_SHORT 0x0100
|
|
||||||
#define SGTL5000_PLL_LOCKED 0x0010
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_CHIP_SHORT_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_LVLADJR_MASK 0x7000
|
|
||||||
#define SGTL5000_LVLADJR_SHIFT 12
|
|
||||||
#define SGTL5000_LVLADJR_WIDTH 3
|
|
||||||
#define SGTL5000_LVLADJL_MASK 0x0700
|
|
||||||
#define SGTL5000_LVLADJL_SHIFT 8
|
|
||||||
#define SGTL5000_LVLADJL_WIDTH 3
|
|
||||||
#define SGTL5000_LVLADJC_MASK 0x0070
|
|
||||||
#define SGTL5000_LVLADJC_SHIFT 4
|
|
||||||
#define SGTL5000_LVLADJC_WIDTH 3
|
|
||||||
#define SGTL5000_LR_SHORT_MOD_MASK 0x000c
|
|
||||||
#define SGTL5000_LR_SHORT_MOD_SHIFT 2
|
|
||||||
#define SGTL5000_LR_SHORT_MOD_WIDTH 2
|
|
||||||
#define SGTL5000_CM_SHORT_MOD_MASK 0x0003
|
|
||||||
#define SGTL5000_CM_SHORT_MOD_SHIFT 0
|
|
||||||
#define SGTL5000_CM_SHORT_MOD_WIDTH 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
*SGTL5000_CHIP_ANA_TEST2
|
|
||||||
*/
|
|
||||||
#define SGTL5000_MONO_DAC 0x1000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_DAP_CTRL
|
|
||||||
*/
|
|
||||||
#define SGTL5000_DAP_MIX_EN 0x0010
|
|
||||||
#define SGTL5000_DAP_EN 0x0001
|
|
||||||
|
|
||||||
#define SGTL5000_SYSCLK 0x00
|
|
||||||
#define SGTL5000_LRCLK 0x01
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SGTL5000_DAP_AUDIO_EQ
|
|
||||||
*/
|
|
||||||
#define SGTL5000_DAP_SEL_PEQ 1
|
|
||||||
#define SGTL5000_DAP_SEL_TONE_CTRL 2
|
|
||||||
#define SGTL5000_DAP_SEL_GEQ 3
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@@ -1,40 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
||||||
/*
|
|
||||||
* tegra_pcm.h - Definitions for Tegra PCM driver
|
|
||||||
*
|
|
||||||
* Author: Stephen Warren <swarren@nvidia.com>
|
|
||||||
* Copyright (C) 2010-2022 - NVIDIA, Inc.
|
|
||||||
*
|
|
||||||
* Based on code copyright/by:
|
|
||||||
*
|
|
||||||
* Copyright (c) 2009-2010, NVIDIA Corporation.
|
|
||||||
* Scott Peterson <speterson@nvidia.com>
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Google, Inc.
|
|
||||||
* Iliyan Malchev <malchev@google.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __TEGRA_PCM_H__
|
|
||||||
#define __TEGRA_PCM_H__
|
|
||||||
|
|
||||||
#include <sound/dmaengine_pcm.h>
|
|
||||||
#include <sound/asound.h>
|
|
||||||
|
|
||||||
int tegra_pcm_construct(struct snd_soc_component *component,
|
|
||||||
struct snd_soc_pcm_runtime *rtd);
|
|
||||||
int tegra_pcm_open(struct snd_soc_component *component,
|
|
||||||
struct snd_pcm_substream *substream);
|
|
||||||
int tegra_pcm_close(struct snd_soc_component *component,
|
|
||||||
struct snd_pcm_substream *substream);
|
|
||||||
int tegra_pcm_hw_params(struct snd_soc_component *component,
|
|
||||||
struct snd_pcm_substream *substream,
|
|
||||||
struct snd_pcm_hw_params *params);
|
|
||||||
snd_pcm_uframes_t tegra_pcm_pointer(struct snd_soc_component *component,
|
|
||||||
struct snd_pcm_substream *substream);
|
|
||||||
int tegra_pcm_platform_register(struct device *dev);
|
|
||||||
int tegra_pcm_platform_register_with_chan_names(struct device *dev,
|
|
||||||
struct snd_dmaengine_pcm_config *config,
|
|
||||||
char *txdmachan, char *rxdmachan);
|
|
||||||
void tegra_pcm_platform_unregister(struct device *dev);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
Reference in New Issue
Block a user