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ASoC:tegra-alt: Add alsa ctls to set SFC o/p rates
This change will add the alsa controls to set SFC i/o rates. SFC from 44.1 to 48 Khz is validated using this change. Find below the list of added alsa controls :- 1)"SFC# output rate" 2)"codec-x rate" '#' = 1,2,3,4 for the respective SFC used. Bug 200090046 Change-Id: Ibbbbcec9b52d5a36b188131fe2cd620e9f3b041f Signed-off-by: Manoj Gangwal <mgangwal@nvidia.com> Reviewed-on: http://git-master/r/729519 (cherry picked from commit f439a370832f5a8515a8be09c977082c89566111) Signed-off-by: Viraj Karandikar <vkarandikar@nvidia.com> Reviewed-on: http://git-master/r/718908
This commit is contained in:
committed by
Sameer Pujar
parent
c7fd07080a
commit
b4d16e4951
@@ -83,6 +83,99 @@ static int tegra210_sfc_suspend(struct device *dev)
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}
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#endif
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u32 coef_44to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
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0x000c6102, /*header*/
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0x0001d727, /* input gain */
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0x00fc2fc7, 0xff9bb27b, 0x001c564c,
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0x00e55557, 0xffcadd5b, 0x003d80ba,
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0x00d13397, 0xfff232f8, 0x00683337,
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0x00000002, /* output gain */
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0x00186102, /* header */
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0x000013d9, /* input gain */
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0x00ebd477, 0xff4ce383, 0x0042049d,
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0x0089c278, 0xff54414d, 0x00531ded,
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0x004a5e07, 0xff53cf41, 0x006efbdc,
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0x00000002, /* output gain */
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0x00235204, /* farrow */
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0x000aaaab,
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0xffaaaaab,
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0xfffaaaab,
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0x00555555,
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0xff600000,
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0xfff55555,
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0x00155555,
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0x00055555,
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0xffeaaaab,
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0x00200000,
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0x00005102, /* header */
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0x0001d029, /* input gain */
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0x00f2a98b, 0xff92aa71, 0x001fcd16,
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0x00ae9004, 0xffb85140, 0x0041813a,
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0x007f8ed1, 0xffd585fc, 0x006a69e6,
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0x00000001 /* output gain */
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};
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u32 coef_16to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
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0x0000a105, /* interpolation + IIR Filter */
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0x00000784, /*input gain */
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0x00cc516e, 0xff2c9639, 0x005ad5b3,
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0x0013ad0d, 0xff3d4799, 0x0063ce75,
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0xffb6f398, 0xff5138d1, 0x006e9e1f,
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0xff9186e5, 0xff5f96a4, 0x0076a86e,
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0xff82089c, 0xff676b81, 0x007b9f8a,
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0xff7c48a5, 0xff6a31e7, 0x007ebb7b,
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0x00000003 /* output gain */
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};
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u32 coef_96to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
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0x00005102,/* header */
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0x0001d727,/* input gain */
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0x00fc2fc7, 0xff9bb27b, 0x001c564c,
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0x00e55557, 0xffcadd5b, 0x003d80ba,
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0x00d13397, 0xfff232f8, 0x00683337,
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0x00000001 /* output gain */
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};
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u32 coef_48to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
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0x000c6102,/* header */
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0x0001d029, /* input gain */
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0x00f2a98b, 0xff92aa71, 0x001fcd16,
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0x00ae9004, 0xffb85140, 0x0041813a,
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0x007f8ed1, 0xffd585fc, 0x006a69e6,
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0x00000002, /* output gain */
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0x001b6103, /* header */
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0x000001e0, /* input gain */
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0x00de44c0, 0xff380b7f, 0x004ffc73,
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0x00494b44, 0xff3d493a, 0x005908bf,
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0xffe9a3c8, 0xff425647, 0x006745f7,
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0xffc42d61, 0xff40a6c7, 0x00776709,
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0x00000002, /* output gain */
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0x00265204, /* farrow */
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0x000aaaab,
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0xffaaaaab,
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0xfffaaaab,
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0x00555555,
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0xff600000,
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0xfff55555,
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0x00155555,
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0x00055555,
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0xffeaaaab,
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0x00200000,
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0x00005102, /* header */
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0x0001d727, /* input gain */
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0x00fc2fc7, 0xff9bb27b, 0x001c564c,
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0x00e55557, 0xffcadd5b, 0x003d80ba,
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0x00d13397, 0xfff232f8, 0x00683337,
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0x00000001 /* output gain */
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};
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/**
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* tegra210_sfc_enable_coef_ram - enables coefficient ram params for a sfc
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* @cif : sfc cif
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* @coef : ptr to coefficients (pass NULL while disabling, i.e. when en = 0)
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* @en : enable/disable flag
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*/
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static int tegra210_sfc_set_dai_sysclk(struct snd_soc_dai *dai,
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int clk_id, unsigned int freq, int dir)
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{
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@@ -169,7 +262,7 @@ static int tegra210_sfc_set_audio_cif(struct tegra210_sfc *sfc,
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cif_conf.audio_channels = channels;
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cif_conf.client_channels = channels;
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_32;
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sfc->soc_data->set_audio_cif(sfc->regmap, reg, &cif_conf);
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@@ -184,6 +277,7 @@ static int tegra210_sfc_in_hw_params(struct snd_pcm_substream *substream,
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struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
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int ret;
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sfc->srate_in = params_rate(params);
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ret = tegra210_sfc_set_audio_cif(sfc, params,
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TEGRA210_SFC_AXBAR_RX_CIF_CTRL);
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if (ret) {
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@@ -192,6 +286,17 @@ static int tegra210_sfc_in_hw_params(struct snd_pcm_substream *substream,
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}
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regmap_write(sfc->regmap, TEGRA210_SFC_AXBAR_RX_FREQ, sfc->srate_in);
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tegra210_xbar_write_ahubram(sfc->regmap,
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TEGRA210_SFC_AHUBRAMCTL_SFC_CTRL,
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TEGRA210_SFC_AHUBRAMCTL_SFC_DATA,
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0, coef_44to48, TEGRA210_SFC_COEF_RAM_DEPTH);
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regmap_update_bits(sfc->regmap,
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TEGRA210_SFC_COEF_RAM,
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TEGRA210_SFC_COEF_RAM_COEF_RAM_EN,
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TEGRA210_SFC_COEF_RAM_COEF_RAM_EN);
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return ret;
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}
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@@ -317,11 +422,13 @@ static const char * const tegra210_sfc_srate_text[] = {
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"192kHz",
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};
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static const struct soc_enum tegra210_sfc_srate =
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SOC_ENUM_SINGLE_EXT(14, tegra210_sfc_srate_text);
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static const struct soc_enum tegra210_sfc_srate_enum =
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SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
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ARRAY_SIZE(tegra210_sfc_srate_text),
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tegra210_sfc_srate_text);
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static const struct snd_kcontrol_new tegra210_sfc_controls[] = {
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SOC_ENUM_EXT("output rate", tegra210_sfc_srate,
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SOC_ENUM_EXT("output rate", tegra210_sfc_srate_enum,
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tegra210_sfc_get_srate, tegra210_sfc_put_srate),
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};
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@@ -801,6 +801,23 @@ static struct of_dev_auxdata tegra210_xbar_auxdata[] = {
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{}
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};
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int tegra210_xbar_set_clock(unsigned long rate)
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{
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int ret = 0;
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ret = clk_set_rate(xbar->clk_parent, rate);
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if (ret)
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pr_info("Failed to set clock rate of pll_a_out0\n");
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ret = clk_set_rate(xbar->clk, rate);
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if (ret)
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pr_info("Failed to set clock rate of ahub\n");
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra210_xbar_set_clock);
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static int tegra210_xbar_registration(struct platform_device *pdev)
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{
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int ret;
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