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ufs: tegra: Remove legacy headers
Linux v5.x kernels are no longer supported and so remove all the legacy UFS related headers for these kernels. Bug 3978622 JIRA LINQPJ14-47 Change-Id: I6e514305d30f93d74bd75fc335db69ced79b3866 Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3349975 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
This commit is contained in:
Jon Hunter
@@ -1,17 +1,11 @@
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// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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// SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include <nvidia/conftest.h>
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#include "ufs-provision.h"
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#include "ufs-provision.h"
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#include "ufs-tegra.h"
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#include "ufs-tegra.h"
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#ifdef CONFIG_DEBUG_FS
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#ifdef CONFIG_DEBUG_FS
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#if defined(NV_UFS_UFSHCD_H_PRESENT)
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#include <ufs/ufshcd.h>
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#include <ufs/ufshcd.h>
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#else
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#include <drivers-private/scsi/ufs/ufshcd.h>
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#endif
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void debugfs_provision_init(struct ufs_hba *hba, struct dentry *device_root)
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void debugfs_provision_init(struct ufs_hba *hba, struct dentry *device_root)
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{
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{
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@@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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// SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include <nvidia/conftest.h>
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#include <nvidia/conftest.h>
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@@ -7,12 +7,8 @@
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#include "ufs-tegra.h"
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#include "ufs-tegra.h"
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#ifdef CONFIG_DEBUG_FS
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#ifdef CONFIG_DEBUG_FS
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#if defined(NV_UFS_UFSHCD_H_PRESENT)
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#include <ufs/ufshcd.h>
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#include <ufs/ufshcd.h>
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#include <drivers-private/scsi/ufs/ufshcd-priv.h>
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#include <drivers-private/scsi/ufs/ufshcd-priv.h>
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#else
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#include <drivers-private/scsi/ufs/ufshcd.h>
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#endif
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#define CHECK_NULL(expr) \
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#define CHECK_NULL(expr) \
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{ \
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{ \
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@@ -1,20 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only
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/* SPDX-License-Identifier: GPL-2.0-only */
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*/
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/* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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// Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#ifndef _UFS_PROVISION_H
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#ifndef _UFS_PROVISION_H
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#define _UFS_PROVISION_H
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#define _UFS_PROVISION_H
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#include <nvidia/conftest.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#if defined(NV_UFS_UFSHCD_H_PRESENT)
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#include <ufs/ufshcd.h>
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#include <ufs/ufshcd.h>
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#else
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#include <drivers-private/scsi/ufs/ufshcd.h>
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#endif
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#ifdef CONFIG_DEBUG_FS
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#include <linux/debugfs.h>
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@@ -27,17 +27,10 @@
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#include <linux/debugfs.h>
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#include <linux/debugfs.h>
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#if defined(NV_UFS_UFSHCD_H_PRESENT)
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#include <drivers-private/scsi/ufs/ufshcd-pltfrm.h>
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#include <drivers-private/scsi/ufs/ufshcd-pltfrm.h>
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#include <ufs/ufshcd.h>
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#include <ufs/ufshcd.h>
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#include <ufs/unipro.h>
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#include <ufs/unipro.h>
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#include <ufs/ufshci.h>
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#include <ufs/ufshci.h>
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#else
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#include <drivers-private/scsi/ufs/ufshcd-pltfrm.h>
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#include <drivers-private/scsi/ufs/ufshcd.h>
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#include <drivers-private/scsi/ufs/unipro.h>
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#include <drivers-private/scsi/ufs/ufshci.h>
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#endif
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#include "ufs-tegra.h"
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#include "ufs-tegra.h"
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#include "ufs-provision.h"
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#include "ufs-provision.h"
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@@ -1,645 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Universal Flash Storage Host controller driver
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* Copyright (C) 2011-2013 Samsung India Software Operations
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*
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* Authors:
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* Santosh Yaraganavi <santosh.sy@samsung.com>
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* Vinayak Holikatti <h.vinayak@samsung.com>
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*/
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#ifndef _UFS_H
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#define _UFS_H
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include <uapi/scsi/scsi_bsg_ufs.h>
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#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
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#define QUERY_DESC_MAX_SIZE 255
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#define QUERY_DESC_MIN_SIZE 2
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#define QUERY_DESC_HDR_SIZE 2
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#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
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(sizeof(struct utp_upiu_header)))
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#define UFS_SENSE_SIZE 18
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#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
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cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
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(byte1 << 8) | (byte0))
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/*
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* UFS device may have standard LUs and LUN id could be from 0x00 to
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* 0x7F. Standard LUs use "Peripheral Device Addressing Format".
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* UFS device may also have the Well Known LUs (also referred as W-LU)
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* which again could be from 0x00 to 0x7F. For W-LUs, device only use
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* the "Extended Addressing Format" which means the W-LUNs would be
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* from 0xc100 (SCSI_W_LUN_BASE) onwards.
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* This means max. LUN number reported from UFS device could be 0xC17F.
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*/
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#define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
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#define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
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#define UFS_UPIU_WLUN_ID (1 << 7)
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#define UFS_RPMB_UNIT 0xC4
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/* WriteBooster buffer is available only for the logical unit from 0 to 7 */
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#define UFS_UPIU_MAX_WB_LUN_ID 8
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/* Well known logical unit id in LUN field of UPIU */
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enum {
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UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
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UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
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UFS_UPIU_BOOT_WLUN = 0xB0,
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UFS_UPIU_RPMB_WLUN = 0xC4,
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};
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/*
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* UFS Protocol Information Unit related definitions
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*/
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/* Task management functions */
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enum {
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UFS_ABORT_TASK = 0x01,
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UFS_ABORT_TASK_SET = 0x02,
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UFS_CLEAR_TASK_SET = 0x04,
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UFS_LOGICAL_RESET = 0x08,
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UFS_QUERY_TASK = 0x80,
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UFS_QUERY_TASK_SET = 0x81,
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};
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/* UTP UPIU Transaction Codes Initiator to Target */
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enum {
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UPIU_TRANSACTION_NOP_OUT = 0x00,
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UPIU_TRANSACTION_COMMAND = 0x01,
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UPIU_TRANSACTION_DATA_OUT = 0x02,
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UPIU_TRANSACTION_TASK_REQ = 0x04,
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UPIU_TRANSACTION_QUERY_REQ = 0x16,
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};
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/* UTP UPIU Transaction Codes Target to Initiator */
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enum {
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UPIU_TRANSACTION_NOP_IN = 0x20,
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UPIU_TRANSACTION_RESPONSE = 0x21,
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UPIU_TRANSACTION_DATA_IN = 0x22,
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UPIU_TRANSACTION_TASK_RSP = 0x24,
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UPIU_TRANSACTION_READY_XFER = 0x31,
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UPIU_TRANSACTION_QUERY_RSP = 0x36,
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UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
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};
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/* UPIU Read/Write flags */
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enum {
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UPIU_CMD_FLAGS_NONE = 0x00,
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UPIU_CMD_FLAGS_WRITE = 0x20,
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UPIU_CMD_FLAGS_READ = 0x40,
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};
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/* UPIU Task Attributes */
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enum {
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UPIU_TASK_ATTR_SIMPLE = 0x00,
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UPIU_TASK_ATTR_ORDERED = 0x01,
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UPIU_TASK_ATTR_HEADQ = 0x02,
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UPIU_TASK_ATTR_ACA = 0x03,
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};
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/* UPIU Query request function */
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enum {
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UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
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UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
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};
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/* Flag idn for Query Requests*/
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enum flag_idn {
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QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
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QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
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QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
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QUERY_FLAG_IDN_BKOPS_EN = 0x04,
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QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
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QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
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QUERY_FLAG_IDN_RESERVED2 = 0x07,
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QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
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QUERY_FLAG_IDN_BUSY_RTC = 0x09,
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QUERY_FLAG_IDN_RESERVED3 = 0x0A,
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QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
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QUERY_FLAG_IDN_WB_EN = 0x0E,
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QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
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QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
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QUERY_FLAG_IDN_HPB_RESET = 0x11,
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QUERY_FLAG_IDN_HPB_EN = 0x12,
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};
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/* Attribute idn for Query requests */
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enum attr_idn {
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QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
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QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
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QUERY_ATTR_IDN_POWER_MODE = 0x02,
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QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
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QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
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QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
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QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
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QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
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QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
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QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
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QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
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QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
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QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
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QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
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QUERY_ATTR_IDN_EE_STATUS = 0x0E,
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QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
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QUERY_ATTR_IDN_CNTX_CONF = 0x10,
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QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
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QUERY_ATTR_IDN_RESERVED2 = 0x12,
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QUERY_ATTR_IDN_RESERVED3 = 0x13,
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QUERY_ATTR_IDN_FFU_STATUS = 0x14,
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QUERY_ATTR_IDN_PSA_STATE = 0x15,
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QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
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QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
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QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
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QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
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QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
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QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
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};
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/* Descriptor idn for Query requests */
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enum desc_idn {
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QUERY_DESC_IDN_DEVICE = 0x0,
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QUERY_DESC_IDN_CONFIGURATION = 0x1,
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QUERY_DESC_IDN_UNIT = 0x2,
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QUERY_DESC_IDN_RFU_0 = 0x3,
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QUERY_DESC_IDN_INTERCONNECT = 0x4,
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QUERY_DESC_IDN_STRING = 0x5,
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QUERY_DESC_IDN_RFU_1 = 0x6,
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QUERY_DESC_IDN_GEOMETRY = 0x7,
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QUERY_DESC_IDN_POWER = 0x8,
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QUERY_DESC_IDN_HEALTH = 0x9,
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QUERY_DESC_IDN_MAX,
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};
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enum desc_header_offset {
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QUERY_DESC_LENGTH_OFFSET = 0x00,
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QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
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};
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/* Unit descriptor parameters offsets in bytes*/
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enum unit_desc_param {
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UNIT_DESC_PARAM_LEN = 0x0,
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UNIT_DESC_PARAM_TYPE = 0x1,
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UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
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UNIT_DESC_PARAM_LU_ENABLE = 0x3,
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UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
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UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
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UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
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UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
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UNIT_DESC_PARAM_MEM_TYPE = 0x8,
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UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
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UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
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UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
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UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
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UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
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UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
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UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
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UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
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UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
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UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
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UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
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UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
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};
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/* Device descriptor parameters offsets in bytes*/
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enum device_desc_param {
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DEVICE_DESC_PARAM_LEN = 0x0,
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DEVICE_DESC_PARAM_TYPE = 0x1,
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DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
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DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
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DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
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DEVICE_DESC_PARAM_PRTCL = 0x5,
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DEVICE_DESC_PARAM_NUM_LU = 0x6,
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DEVICE_DESC_PARAM_NUM_WLU = 0x7,
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DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
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DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
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DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
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DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
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|
||||||
DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
|
|
||||||
DEVICE_DESC_PARAM_SEC_LU = 0xD,
|
|
||||||
DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
|
|
||||||
DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
|
|
||||||
DEVICE_DESC_PARAM_SPEC_VER = 0x10,
|
|
||||||
DEVICE_DESC_PARAM_MANF_DATE = 0x12,
|
|
||||||
DEVICE_DESC_PARAM_MANF_NAME = 0x14,
|
|
||||||
DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
|
|
||||||
DEVICE_DESC_PARAM_SN = 0x16,
|
|
||||||
DEVICE_DESC_PARAM_OEM_ID = 0x17,
|
|
||||||
DEVICE_DESC_PARAM_MANF_ID = 0x18,
|
|
||||||
DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
|
|
||||||
DEVICE_DESC_PARAM_UD_LEN = 0x1B,
|
|
||||||
DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
|
|
||||||
DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
|
|
||||||
DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
|
|
||||||
DEVICE_DESC_PARAM_FFU_TMT = 0x20,
|
|
||||||
DEVICE_DESC_PARAM_Q_DPTH = 0x21,
|
|
||||||
DEVICE_DESC_PARAM_DEV_VER = 0x22,
|
|
||||||
DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
|
|
||||||
DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
|
|
||||||
DEVICE_DESC_PARAM_PSA_TMT = 0x29,
|
|
||||||
DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
|
|
||||||
DEVICE_DESC_PARAM_HPB_VER = 0x40,
|
|
||||||
DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
|
|
||||||
DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
|
|
||||||
DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
|
|
||||||
DEVICE_DESC_PARAM_WB_TYPE = 0x54,
|
|
||||||
DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Interconnect descriptor parameters offsets in bytes*/
|
|
||||||
enum interconnect_desc_param {
|
|
||||||
INTERCONNECT_DESC_PARAM_LEN = 0x0,
|
|
||||||
INTERCONNECT_DESC_PARAM_TYPE = 0x1,
|
|
||||||
INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
|
|
||||||
INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Geometry descriptor parameters offsets in bytes*/
|
|
||||||
enum geometry_desc_param {
|
|
||||||
GEOMETRY_DESC_PARAM_LEN = 0x0,
|
|
||||||
GEOMETRY_DESC_PARAM_TYPE = 0x1,
|
|
||||||
GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
|
|
||||||
GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
|
|
||||||
GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
|
|
||||||
GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
|
|
||||||
GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
|
|
||||||
GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
|
|
||||||
GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
|
|
||||||
GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
|
|
||||||
GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
|
|
||||||
GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
|
|
||||||
GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
|
|
||||||
GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
|
|
||||||
GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
|
|
||||||
GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
|
|
||||||
GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
|
|
||||||
GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
|
|
||||||
GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
|
|
||||||
GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
|
|
||||||
GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
|
|
||||||
GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
|
|
||||||
GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
|
|
||||||
GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
|
|
||||||
GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
|
|
||||||
GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
|
|
||||||
GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
|
|
||||||
GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Health descriptor parameters offsets in bytes*/
|
|
||||||
enum health_desc_param {
|
|
||||||
HEALTH_DESC_PARAM_LEN = 0x0,
|
|
||||||
HEALTH_DESC_PARAM_TYPE = 0x1,
|
|
||||||
HEALTH_DESC_PARAM_EOL_INFO = 0x2,
|
|
||||||
HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
|
|
||||||
HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* WriteBooster buffer mode */
|
|
||||||
enum {
|
|
||||||
WB_BUF_MODE_LU_DEDICATED = 0x0,
|
|
||||||
WB_BUF_MODE_SHARED = 0x1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Logical Unit Write Protect
|
|
||||||
* 00h: LU not write protected
|
|
||||||
* 01h: LU write protected when fPowerOnWPEn =1
|
|
||||||
* 02h: LU permanently write protected when fPermanentWPEn =1
|
|
||||||
*/
|
|
||||||
enum ufs_lu_wp_type {
|
|
||||||
UFS_LU_NO_WP = 0x00,
|
|
||||||
UFS_LU_POWER_ON_WP = 0x01,
|
|
||||||
UFS_LU_PERM_WP = 0x02,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* bActiveICCLevel parameter current units */
|
|
||||||
enum {
|
|
||||||
UFSHCD_NANO_AMP = 0,
|
|
||||||
UFSHCD_MICRO_AMP = 1,
|
|
||||||
UFSHCD_MILI_AMP = 2,
|
|
||||||
UFSHCD_AMP = 3,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Possible values for dExtendedUFSFeaturesSupport */
|
|
||||||
enum {
|
|
||||||
UFS_DEV_HPB_SUPPORT = BIT(7),
|
|
||||||
UFS_DEV_WRITE_BOOSTER_SUP = BIT(8),
|
|
||||||
};
|
|
||||||
#define UFS_DEV_HPB_SUPPORT_VERSION 0x310
|
|
||||||
|
|
||||||
#define POWER_DESC_MAX_ACTV_ICC_LVLS 16
|
|
||||||
|
|
||||||
/* Attribute bActiveICCLevel parameter bit masks definitions */
|
|
||||||
#define ATTR_ICC_LVL_UNIT_OFFSET 14
|
|
||||||
#define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
|
|
||||||
#define ATTR_ICC_LVL_VALUE_MASK 0x3FF
|
|
||||||
|
|
||||||
/* Power descriptor parameters offsets in bytes */
|
|
||||||
enum power_desc_param_offset {
|
|
||||||
PWR_DESC_LEN = 0x0,
|
|
||||||
PWR_DESC_TYPE = 0x1,
|
|
||||||
PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2,
|
|
||||||
PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22,
|
|
||||||
PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Exception event mask values */
|
|
||||||
enum {
|
|
||||||
MASK_EE_STATUS = 0xFFFF,
|
|
||||||
MASK_EE_DYNCAP_EVENT = BIT(0),
|
|
||||||
MASK_EE_SYSPOOL_EVENT = BIT(1),
|
|
||||||
MASK_EE_URGENT_BKOPS = BIT(2),
|
|
||||||
MASK_EE_TOO_HIGH_TEMP = BIT(3),
|
|
||||||
MASK_EE_TOO_LOW_TEMP = BIT(4),
|
|
||||||
MASK_EE_WRITEBOOSTER_EVENT = BIT(5),
|
|
||||||
MASK_EE_PERFORMANCE_THROTTLING = BIT(6),
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Background operation status */
|
|
||||||
enum bkops_status {
|
|
||||||
BKOPS_STATUS_NO_OP = 0x0,
|
|
||||||
BKOPS_STATUS_NON_CRITICAL = 0x1,
|
|
||||||
BKOPS_STATUS_PERF_IMPACT = 0x2,
|
|
||||||
BKOPS_STATUS_CRITICAL = 0x3,
|
|
||||||
BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP QUERY Transaction Specific Fields OpCode */
|
|
||||||
enum query_opcode {
|
|
||||||
UPIU_QUERY_OPCODE_NOP = 0x0,
|
|
||||||
UPIU_QUERY_OPCODE_READ_DESC = 0x1,
|
|
||||||
UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
|
|
||||||
UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
|
|
||||||
UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
|
|
||||||
UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
|
|
||||||
UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
|
|
||||||
UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
|
|
||||||
UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* bRefClkFreq attribute values */
|
|
||||||
enum ufs_ref_clk_freq {
|
|
||||||
REF_CLK_FREQ_19_2_MHZ = 0,
|
|
||||||
REF_CLK_FREQ_26_MHZ = 1,
|
|
||||||
REF_CLK_FREQ_38_4_MHZ = 2,
|
|
||||||
REF_CLK_FREQ_52_MHZ = 3,
|
|
||||||
REF_CLK_FREQ_INVAL = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ufs_ref_clk {
|
|
||||||
unsigned long freq_hz;
|
|
||||||
enum ufs_ref_clk_freq val;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Query response result code */
|
|
||||||
enum {
|
|
||||||
QUERY_RESULT_SUCCESS = 0x00,
|
|
||||||
QUERY_RESULT_NOT_READABLE = 0xF6,
|
|
||||||
QUERY_RESULT_NOT_WRITEABLE = 0xF7,
|
|
||||||
QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
|
|
||||||
QUERY_RESULT_INVALID_LENGTH = 0xF9,
|
|
||||||
QUERY_RESULT_INVALID_VALUE = 0xFA,
|
|
||||||
QUERY_RESULT_INVALID_SELECTOR = 0xFB,
|
|
||||||
QUERY_RESULT_INVALID_INDEX = 0xFC,
|
|
||||||
QUERY_RESULT_INVALID_IDN = 0xFD,
|
|
||||||
QUERY_RESULT_INVALID_OPCODE = 0xFE,
|
|
||||||
QUERY_RESULT_GENERAL_FAILURE = 0xFF,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP Transfer Request Command Type (CT) */
|
|
||||||
enum {
|
|
||||||
UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
|
|
||||||
UPIU_COMMAND_SET_TYPE_UFS = 0x1,
|
|
||||||
UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP Transfer Request Command Offset */
|
|
||||||
#define UPIU_COMMAND_TYPE_OFFSET 28
|
|
||||||
|
|
||||||
/* Offset of the response code in the UPIU header */
|
|
||||||
#define UPIU_RSP_CODE_OFFSET 8
|
|
||||||
|
|
||||||
enum {
|
|
||||||
MASK_SCSI_STATUS = 0xFF,
|
|
||||||
MASK_TASK_RESPONSE = 0xFF00,
|
|
||||||
MASK_RSP_UPIU_RESULT = 0xFFFF,
|
|
||||||
MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
|
|
||||||
MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
|
|
||||||
MASK_RSP_EXCEPTION_EVENT = 0x10000,
|
|
||||||
MASK_TM_SERVICE_RESP = 0xFF,
|
|
||||||
MASK_TM_FUNC = 0xFF,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Task management service response */
|
|
||||||
enum {
|
|
||||||
UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
|
|
||||||
UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
|
|
||||||
UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
|
|
||||||
UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
|
|
||||||
UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UFS device power modes */
|
|
||||||
enum ufs_dev_pwr_mode {
|
|
||||||
UFS_ACTIVE_PWR_MODE = 1,
|
|
||||||
UFS_SLEEP_PWR_MODE = 2,
|
|
||||||
UFS_POWERDOWN_PWR_MODE = 3,
|
|
||||||
UFS_DEEPSLEEP_PWR_MODE = 4,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_cmd_rsp - Response UPIU structure
|
|
||||||
* @residual_transfer_count: Residual transfer count DW-3
|
|
||||||
* @reserved: Reserved double words DW-4 to DW-7
|
|
||||||
* @sense_data_len: Sense data length DW-8 U16
|
|
||||||
* @sense_data: Sense data field DW-8 to DW-12
|
|
||||||
*/
|
|
||||||
struct utp_cmd_rsp {
|
|
||||||
__be32 residual_transfer_count;
|
|
||||||
__be32 reserved[4];
|
|
||||||
__be16 sense_data_len;
|
|
||||||
u8 sense_data[UFS_SENSE_SIZE];
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ufshpb_active_field {
|
|
||||||
__be16 active_rgn;
|
|
||||||
__be16 active_srgn;
|
|
||||||
};
|
|
||||||
#define HPB_ACT_FIELD_SIZE 4
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_hpb_rsp - Response UPIU structure
|
|
||||||
* @residual_transfer_count: Residual transfer count DW-3
|
|
||||||
* @reserved1: Reserved double words DW-4 to DW-7
|
|
||||||
* @sense_data_len: Sense data length DW-8 U16
|
|
||||||
* @desc_type: Descriptor type of sense data
|
|
||||||
* @additional_len: Additional length of sense data
|
|
||||||
* @hpb_op: HPB operation type
|
|
||||||
* @lun: LUN of response UPIU
|
|
||||||
* @active_rgn_cnt: Active region count
|
|
||||||
* @inactive_rgn_cnt: Inactive region count
|
|
||||||
* @hpb_active_field: Recommended to read HPB region and subregion
|
|
||||||
* @hpb_inactive_field: To be inactivated HPB region and subregion
|
|
||||||
*/
|
|
||||||
struct utp_hpb_rsp {
|
|
||||||
__be32 residual_transfer_count;
|
|
||||||
__be32 reserved1[4];
|
|
||||||
__be16 sense_data_len;
|
|
||||||
u8 desc_type;
|
|
||||||
u8 additional_len;
|
|
||||||
u8 hpb_op;
|
|
||||||
u8 lun;
|
|
||||||
u8 active_rgn_cnt;
|
|
||||||
u8 inactive_rgn_cnt;
|
|
||||||
struct ufshpb_active_field hpb_active_field[2];
|
|
||||||
__be16 hpb_inactive_field[2];
|
|
||||||
};
|
|
||||||
#define UTP_HPB_RSP_SIZE 40
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_upiu_rsp - general upiu response structure
|
|
||||||
* @header: UPIU header structure DW-0 to DW-2
|
|
||||||
* @sr: fields structure for scsi command DW-3 to DW-12
|
|
||||||
* @qr: fields structure for query request DW-3 to DW-7
|
|
||||||
*/
|
|
||||||
struct utp_upiu_rsp {
|
|
||||||
struct utp_upiu_header header;
|
|
||||||
union {
|
|
||||||
struct utp_cmd_rsp sr;
|
|
||||||
struct utp_hpb_rsp hr;
|
|
||||||
struct utp_upiu_query qr;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct ufs_query_req - parameters for building a query request
|
|
||||||
* @query_func: UPIU header query function
|
|
||||||
* @upiu_req: the query request data
|
|
||||||
*/
|
|
||||||
struct ufs_query_req {
|
|
||||||
u8 query_func;
|
|
||||||
struct utp_upiu_query upiu_req;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct ufs_query_resp - UPIU QUERY
|
|
||||||
* @response: device response code
|
|
||||||
* @upiu_res: query response data
|
|
||||||
*/
|
|
||||||
struct ufs_query_res {
|
|
||||||
u8 response;
|
|
||||||
struct utp_upiu_query upiu_res;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define UFS_VREG_VCC_MIN_UV 2700000 /* uV */
|
|
||||||
#define UFS_VREG_VCC_MAX_UV 3600000 /* uV */
|
|
||||||
#define UFS_VREG_VCC_1P8_MIN_UV 1700000 /* uV */
|
|
||||||
#define UFS_VREG_VCC_1P8_MAX_UV 1950000 /* uV */
|
|
||||||
#define UFS_VREG_VCCQ_MIN_UV 1140000 /* uV */
|
|
||||||
#define UFS_VREG_VCCQ_MAX_UV 1260000 /* uV */
|
|
||||||
#define UFS_VREG_VCCQ2_MIN_UV 1700000 /* uV */
|
|
||||||
#define UFS_VREG_VCCQ2_MAX_UV 1950000 /* uV */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* VCCQ & VCCQ2 current requirement when UFS device is in sleep state
|
|
||||||
* and link is in Hibern8 state.
|
|
||||||
*/
|
|
||||||
#define UFS_VREG_LPM_LOAD_UA 1000 /* uA */
|
|
||||||
|
|
||||||
struct ufs_vreg {
|
|
||||||
struct regulator *reg;
|
|
||||||
const char *name;
|
|
||||||
bool always_on;
|
|
||||||
bool enabled;
|
|
||||||
int min_uV;
|
|
||||||
int max_uV;
|
|
||||||
int max_uA;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ufs_vreg_info {
|
|
||||||
struct ufs_vreg *vcc;
|
|
||||||
struct ufs_vreg *vccq;
|
|
||||||
struct ufs_vreg *vccq2;
|
|
||||||
struct ufs_vreg *vdd_hba;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ufs_dev_info {
|
|
||||||
bool f_power_on_wp_en;
|
|
||||||
/* Keeps information if any of the LU is power on write protected */
|
|
||||||
bool is_lu_power_on_wp;
|
|
||||||
/* Maximum number of general LU supported by the UFS device */
|
|
||||||
u8 max_lu_supported;
|
|
||||||
u16 wmanufacturerid;
|
|
||||||
/*UFS device Product Name */
|
|
||||||
u8 *model;
|
|
||||||
u16 wspecversion;
|
|
||||||
u32 clk_gating_wait_us;
|
|
||||||
|
|
||||||
/* UFS HPB related flag */
|
|
||||||
bool hpb_enabled;
|
|
||||||
|
|
||||||
/* UFS WB related flags */
|
|
||||||
bool wb_enabled;
|
|
||||||
bool wb_buf_flush_enabled;
|
|
||||||
u8 wb_dedicated_lu;
|
|
||||||
u8 wb_buffer_type;
|
|
||||||
|
|
||||||
bool b_rpm_dev_flush_capable;
|
|
||||||
u8 b_presrv_uspc_en;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This enum is used in string mapping in include/trace/events/ufs.h.
|
|
||||||
*/
|
|
||||||
enum ufs_trace_str_t {
|
|
||||||
UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP,
|
|
||||||
UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR,
|
|
||||||
UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Transaction Specific Fields (TSF) type in the UPIU package, this enum is
|
|
||||||
* used in include/trace/events/ufs.h for UFS command trace.
|
|
||||||
*/
|
|
||||||
enum ufs_trace_tsf_t {
|
|
||||||
UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* ufs_is_valid_unit_desc_lun - checks if the given LUN has a unit descriptor
|
|
||||||
* @dev_info: pointer of instance of struct ufs_dev_info
|
|
||||||
* @lun: LU number to check
|
|
||||||
* @return: true if the lun has a matching unit descriptor, false otherwise
|
|
||||||
*/
|
|
||||||
static inline bool ufs_is_valid_unit_desc_lun(struct ufs_dev_info *dev_info,
|
|
||||||
u8 lun, u8 param_offset)
|
|
||||||
{
|
|
||||||
if (!dev_info || !dev_info->max_lu_supported) {
|
|
||||||
pr_err("Max General LU supported by UFS isn't initialized\n");
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
/* WB is available only for the logical unit from 0 to 7 */
|
|
||||||
if (param_offset == UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS)
|
|
||||||
return lun < UFS_UPIU_MAX_WB_LUN_ID;
|
|
||||||
return lun == UFS_UPIU_RPMB_WLUN || (lun < dev_info->max_lu_supported);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* End of Header */
|
|
||||||
@@ -1,125 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
||||||
/*
|
|
||||||
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _UFS_QUIRKS_H_
|
|
||||||
#define _UFS_QUIRKS_H_
|
|
||||||
|
|
||||||
/* return true if s1 is a prefix of s2 */
|
|
||||||
#define STR_PRFX_EQUAL(s1, s2) !strncmp(s1, s2, strlen(s1))
|
|
||||||
|
|
||||||
#define UFS_ANY_VENDOR 0xFFFF
|
|
||||||
#define UFS_ANY_MODEL "ANY_MODEL"
|
|
||||||
|
|
||||||
#define UFS_VENDOR_MICRON 0x12C
|
|
||||||
#define UFS_VENDOR_SAMSUNG 0x1CE
|
|
||||||
#define UFS_VENDOR_SKHYNIX 0x1AD
|
|
||||||
#define UFS_VENDOR_TOSHIBA 0x198
|
|
||||||
#define UFS_VENDOR_WDC 0x145
|
|
||||||
|
|
||||||
/**
|
|
||||||
* ufs_dev_fix - ufs device quirk info
|
|
||||||
* @card: ufs card details
|
|
||||||
* @quirk: device quirk
|
|
||||||
*/
|
|
||||||
struct ufs_dev_fix {
|
|
||||||
u16 wmanufacturerid;
|
|
||||||
u8 *model;
|
|
||||||
unsigned int quirk;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define END_FIX { }
|
|
||||||
|
|
||||||
/* add specific device quirk */
|
|
||||||
#define UFS_FIX(_vendor, _model, _quirk) { \
|
|
||||||
.wmanufacturerid = (_vendor),\
|
|
||||||
.model = (_model), \
|
|
||||||
.quirk = (_quirk), \
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some vendor's UFS device sends back to back NACs for the DL data frames
|
|
||||||
* causing the host controller to raise the DFES error status. Sometimes
|
|
||||||
* such UFS devices send back to back NAC without waiting for new
|
|
||||||
* retransmitted DL frame from the host and in such cases it might be possible
|
|
||||||
* the Host UniPro goes into bad state without raising the DFES error
|
|
||||||
* interrupt. If this happens then all the pending commands would timeout
|
|
||||||
* only after respective SW command (which is generally too large).
|
|
||||||
*
|
|
||||||
* We can workaround such device behaviour like this:
|
|
||||||
* - As soon as SW sees the DL NAC error, it should schedule the error handler
|
|
||||||
* - Error handler would sleep for 50ms to see if there are any fatal errors
|
|
||||||
* raised by UFS controller.
|
|
||||||
* - If there are fatal errors then SW does normal error recovery.
|
|
||||||
* - If there are no fatal errors then SW sends the NOP command to device
|
|
||||||
* to check if link is alive.
|
|
||||||
* - If NOP command times out, SW does normal error recovery
|
|
||||||
* - If NOP command succeed, skip the error handling.
|
|
||||||
*
|
|
||||||
* If DL NAC error is seen multiple times with some vendor's UFS devices then
|
|
||||||
* enable this quirk to initiate quick error recovery and also silence related
|
|
||||||
* error logs to reduce spamming of kernel logs.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS (1 << 2)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Few Toshiba UFS device models advertise RX_MIN_ACTIVATETIME_CAPABILITY as
|
|
||||||
* 600us which may not be enough for reliable hibern8 exit hardware sequence
|
|
||||||
* from UFS device.
|
|
||||||
* To workaround this issue, host should set its PA_TACTIVATE time to 1ms even
|
|
||||||
* if device advertises RX_MIN_ACTIVATETIME_CAPABILITY less than 1ms.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_PA_TACTIVATE (1 << 4)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* It seems some UFS devices may keep drawing more than sleep current
|
|
||||||
* (atleast for 500us) from UFS rails (especially from VCCQ rail).
|
|
||||||
* To avoid this situation, add 2ms delay before putting these UFS
|
|
||||||
* rails in LPM mode.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM (1 << 6)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some UFS devices require host PA_TACTIVATE to be lower than device
|
|
||||||
* PA_TACTIVATE, enabling this quirk ensure this.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE (1 << 7)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The max. value PA_SaveConfigTime is 250 (10us) but this is not enough for
|
|
||||||
* some vendors.
|
|
||||||
* Gear switch from PWM to HS may fail even with this max. PA_SaveConfigTime.
|
|
||||||
* Gear switch can be issued by host controller as an error recovery and any
|
|
||||||
* software delay will not help on this case so we need to increase
|
|
||||||
* PA_SaveConfigTime to >32us as per vendor recommendation.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME (1 << 8)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some UFS devices require VS_DebugSaveConfigTime is 0x10,
|
|
||||||
* enabling this quirk ensure this.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME (1 << 9)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some pre-3.1 UFS devices can support extended features by upgrading
|
|
||||||
* the firmware. Enable this quirk to make UFS core driver probe and enable
|
|
||||||
* supported features on such devices.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES (1 << 10)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some UFS devices require delay after VCC power rail is turned-off.
|
|
||||||
* Enable this quirk to introduce 5ms delays after VCC power-off during
|
|
||||||
* suspend flow.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_DELAY_AFTER_LPM (1 << 11)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some UFS devices require L2P entry should be swapped before being sent to the
|
|
||||||
* UFS device for HPB READ command.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ (1 << 12)
|
|
||||||
|
|
||||||
#endif /* UFS_QUIRKS_H_ */
|
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -1,506 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
||||||
/*
|
|
||||||
* Universal Flash Storage Host controller driver
|
|
||||||
* Copyright (C) 2011-2013 Samsung India Software Operations
|
|
||||||
*
|
|
||||||
* Authors:
|
|
||||||
* Santosh Yaraganavi <santosh.sy@samsung.com>
|
|
||||||
* Vinayak Holikatti <h.vinayak@samsung.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _UFSHCI_H
|
|
||||||
#define _UFSHCI_H
|
|
||||||
|
|
||||||
enum {
|
|
||||||
TASK_REQ_UPIU_SIZE_DWORDS = 8,
|
|
||||||
TASK_RSP_UPIU_SIZE_DWORDS = 8,
|
|
||||||
ALIGNED_UPIU_SIZE = 512,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UFSHCI Registers */
|
|
||||||
enum {
|
|
||||||
REG_CONTROLLER_CAPABILITIES = 0x00,
|
|
||||||
REG_UFS_VERSION = 0x08,
|
|
||||||
REG_CONTROLLER_DEV_ID = 0x10,
|
|
||||||
REG_CONTROLLER_PROD_ID = 0x14,
|
|
||||||
REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
|
|
||||||
REG_INTERRUPT_STATUS = 0x20,
|
|
||||||
REG_INTERRUPT_ENABLE = 0x24,
|
|
||||||
REG_CONTROLLER_STATUS = 0x30,
|
|
||||||
REG_CONTROLLER_ENABLE = 0x34,
|
|
||||||
REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
|
|
||||||
REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
|
|
||||||
REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
|
|
||||||
REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
|
|
||||||
REG_UIC_ERROR_CODE_DME = 0x48,
|
|
||||||
REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
|
|
||||||
REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
|
|
||||||
REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
|
|
||||||
REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
|
|
||||||
REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
|
|
||||||
REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
|
|
||||||
REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
|
|
||||||
REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
|
|
||||||
REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
|
|
||||||
REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
|
|
||||||
REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
|
|
||||||
REG_UIC_COMMAND = 0x90,
|
|
||||||
REG_UIC_COMMAND_ARG_1 = 0x94,
|
|
||||||
REG_UIC_COMMAND_ARG_2 = 0x98,
|
|
||||||
REG_UIC_COMMAND_ARG_3 = 0x9C,
|
|
||||||
|
|
||||||
UFSHCI_REG_SPACE_SIZE = 0xA0,
|
|
||||||
|
|
||||||
REG_UFS_CCAP = 0x100,
|
|
||||||
REG_UFS_CRYPTOCAP = 0x104,
|
|
||||||
|
|
||||||
UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Controller capability masks */
|
|
||||||
enum {
|
|
||||||
MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
|
|
||||||
MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
|
|
||||||
MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
|
|
||||||
MASK_64_ADDRESSING_SUPPORT = 0x01000000,
|
|
||||||
MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
|
|
||||||
MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
|
|
||||||
MASK_CRYPTO_SUPPORT = 0x10000000,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define UFS_MASK(mask, offset) ((mask) << (offset))
|
|
||||||
|
|
||||||
/* UFS Version 08h */
|
|
||||||
#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
|
|
||||||
#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Controller UFSHCI version
|
|
||||||
* - 2.x and newer use the following scheme:
|
|
||||||
* major << 8 + minor << 4
|
|
||||||
* - 1.x has been converted to match this in
|
|
||||||
* ufshcd_get_ufs_version()
|
|
||||||
*/
|
|
||||||
static inline u32 ufshci_version(u32 major, u32 minor)
|
|
||||||
{
|
|
||||||
return (major << 8) + (minor << 4);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* HCDDID - Host Controller Identification Descriptor
|
|
||||||
* - Device ID and Device Class 10h
|
|
||||||
*/
|
|
||||||
#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
|
|
||||||
#define DEVICE_ID UFS_MASK(0xFF, 24)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* HCPMID - Host Controller Identification Descriptor
|
|
||||||
* - Product/Manufacturer ID 14h
|
|
||||||
*/
|
|
||||||
#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
|
|
||||||
#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
|
|
||||||
|
|
||||||
/* AHIT - Auto-Hibernate Idle Timer */
|
|
||||||
#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
|
|
||||||
#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
|
|
||||||
#define UFSHCI_AHIBERN8_SCALE_FACTOR 10
|
|
||||||
#define UFSHCI_AHIBERN8_MAX (1023 * 100000)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IS - Interrupt Status - 20h
|
|
||||||
*/
|
|
||||||
#define UTP_TRANSFER_REQ_COMPL 0x1
|
|
||||||
#define UIC_DME_END_PT_RESET 0x2
|
|
||||||
#define UIC_ERROR 0x4
|
|
||||||
#define UIC_TEST_MODE 0x8
|
|
||||||
#define UIC_POWER_MODE 0x10
|
|
||||||
#define UIC_HIBERNATE_EXIT 0x20
|
|
||||||
#define UIC_HIBERNATE_ENTER 0x40
|
|
||||||
#define UIC_LINK_LOST 0x80
|
|
||||||
#define UIC_LINK_STARTUP 0x100
|
|
||||||
#define UTP_TASK_REQ_COMPL 0x200
|
|
||||||
#define UIC_COMMAND_COMPL 0x400
|
|
||||||
#define DEVICE_FATAL_ERROR 0x800
|
|
||||||
#define CONTROLLER_FATAL_ERROR 0x10000
|
|
||||||
#define SYSTEM_BUS_FATAL_ERROR 0x20000
|
|
||||||
#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
|
|
||||||
|
|
||||||
#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
|
|
||||||
UIC_HIBERNATE_EXIT)
|
|
||||||
|
|
||||||
#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
|
|
||||||
UIC_POWER_MODE)
|
|
||||||
|
|
||||||
#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
|
|
||||||
|
|
||||||
#define UFSHCD_ERROR_MASK (UIC_ERROR |\
|
|
||||||
DEVICE_FATAL_ERROR |\
|
|
||||||
CONTROLLER_FATAL_ERROR |\
|
|
||||||
SYSTEM_BUS_FATAL_ERROR |\
|
|
||||||
CRYPTO_ENGINE_FATAL_ERROR)
|
|
||||||
|
|
||||||
#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
|
|
||||||
CONTROLLER_FATAL_ERROR |\
|
|
||||||
SYSTEM_BUS_FATAL_ERROR |\
|
|
||||||
CRYPTO_ENGINE_FATAL_ERROR)
|
|
||||||
|
|
||||||
/* HCS - Host Controller Status 30h */
|
|
||||||
#define DEVICE_PRESENT 0x1
|
|
||||||
#define UTP_TRANSFER_REQ_LIST_READY 0x2
|
|
||||||
#define UTP_TASK_REQ_LIST_READY 0x4
|
|
||||||
#define UIC_COMMAND_READY 0x8
|
|
||||||
#define HOST_ERROR_INDICATOR 0x10
|
|
||||||
#define DEVICE_ERROR_INDICATOR 0x20
|
|
||||||
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
|
|
||||||
|
|
||||||
#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
|
|
||||||
UTP_TASK_REQ_LIST_READY |\
|
|
||||||
UIC_COMMAND_READY)
|
|
||||||
|
|
||||||
enum {
|
|
||||||
PWR_OK = 0x0,
|
|
||||||
PWR_LOCAL = 0x01,
|
|
||||||
PWR_REMOTE = 0x02,
|
|
||||||
PWR_BUSY = 0x03,
|
|
||||||
PWR_ERROR_CAP = 0x04,
|
|
||||||
PWR_FATAL_ERROR = 0x05,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* HCE - Host Controller Enable 34h */
|
|
||||||
#define CONTROLLER_ENABLE 0x1
|
|
||||||
#define CONTROLLER_DISABLE 0x0
|
|
||||||
#define CRYPTO_GENERAL_ENABLE 0x2
|
|
||||||
|
|
||||||
/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
|
|
||||||
#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
|
|
||||||
#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
|
|
||||||
#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
|
|
||||||
#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
|
|
||||||
|
|
||||||
/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
|
|
||||||
|
|
||||||
/* UECN - Host UIC Error Code Network Layer 40h */
|
|
||||||
#define UIC_NETWORK_LAYER_ERROR 0x80000000
|
|
||||||
#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
|
|
||||||
#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
|
|
||||||
#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
|
|
||||||
#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
|
|
||||||
|
|
||||||
/* UECT - Host UIC Error Code Transport Layer 44h */
|
|
||||||
#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
|
|
||||||
#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
|
|
||||||
#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
|
|
||||||
#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
|
|
||||||
#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
|
|
||||||
#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
|
|
||||||
#define UIC_TRANSPORT_BAD_TC 0x10
|
|
||||||
#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
|
|
||||||
#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
|
|
||||||
|
|
||||||
/* UECDME - Host UIC Error Code DME 48h */
|
|
||||||
#define UIC_DME_ERROR 0x80000000
|
|
||||||
#define UIC_DME_ERROR_CODE_MASK 0x1
|
|
||||||
|
|
||||||
/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
|
|
||||||
#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
|
|
||||||
#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
|
|
||||||
#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
|
|
||||||
#define INT_AGGR_STATUS_BIT 0x100000
|
|
||||||
#define INT_AGGR_PARAM_WRITE 0x1000000
|
|
||||||
#define INT_AGGR_ENABLE 0x80000000
|
|
||||||
|
|
||||||
/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
|
|
||||||
#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
|
|
||||||
|
|
||||||
/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
|
|
||||||
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
|
|
||||||
|
|
||||||
/* UICCMD - UIC Command */
|
|
||||||
#define COMMAND_OPCODE_MASK 0xFF
|
|
||||||
#define GEN_SELECTOR_INDEX_MASK 0xFFFF
|
|
||||||
|
|
||||||
#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
|
|
||||||
#define RESET_LEVEL 0xFF
|
|
||||||
|
|
||||||
#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
|
|
||||||
#define CONFIG_RESULT_CODE_MASK 0xFF
|
|
||||||
#define GENERIC_ERROR_CODE_MASK 0xFF
|
|
||||||
|
|
||||||
/* GenSelectorIndex calculation macros for M-PHY attributes */
|
|
||||||
#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
|
|
||||||
#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
|
|
||||||
|
|
||||||
#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
|
|
||||||
((sel) & 0xFFFF))
|
|
||||||
#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
|
|
||||||
#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
|
|
||||||
#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
|
|
||||||
|
|
||||||
/* Link Status*/
|
|
||||||
enum link_status {
|
|
||||||
UFSHCD_LINK_IS_DOWN = 1,
|
|
||||||
UFSHCD_LINK_IS_UP = 2,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UIC Commands */
|
|
||||||
enum uic_cmd_dme {
|
|
||||||
UIC_CMD_DME_GET = 0x01,
|
|
||||||
UIC_CMD_DME_SET = 0x02,
|
|
||||||
UIC_CMD_DME_PEER_GET = 0x03,
|
|
||||||
UIC_CMD_DME_PEER_SET = 0x04,
|
|
||||||
UIC_CMD_DME_POWERON = 0x10,
|
|
||||||
UIC_CMD_DME_POWEROFF = 0x11,
|
|
||||||
UIC_CMD_DME_ENABLE = 0x12,
|
|
||||||
UIC_CMD_DME_RESET = 0x14,
|
|
||||||
UIC_CMD_DME_END_PT_RST = 0x15,
|
|
||||||
UIC_CMD_DME_LINK_STARTUP = 0x16,
|
|
||||||
UIC_CMD_DME_HIBER_ENTER = 0x17,
|
|
||||||
UIC_CMD_DME_HIBER_EXIT = 0x18,
|
|
||||||
UIC_CMD_DME_TEST_MODE = 0x1A,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UIC Config result code / Generic error code */
|
|
||||||
enum {
|
|
||||||
UIC_CMD_RESULT_SUCCESS = 0x00,
|
|
||||||
UIC_CMD_RESULT_INVALID_ATTR = 0x01,
|
|
||||||
UIC_CMD_RESULT_FAILURE = 0x01,
|
|
||||||
UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
|
|
||||||
UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
|
|
||||||
UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
|
|
||||||
UIC_CMD_RESULT_BAD_INDEX = 0x05,
|
|
||||||
UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
|
|
||||||
UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
|
|
||||||
UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
|
|
||||||
UIC_CMD_RESULT_BUSY = 0x09,
|
|
||||||
UIC_CMD_RESULT_DME_FAILURE = 0x0A,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define MASK_UIC_COMMAND_RESULT 0xFF
|
|
||||||
|
|
||||||
#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
|
|
||||||
#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
|
|
||||||
|
|
||||||
/* Interrupt disable masks */
|
|
||||||
enum {
|
|
||||||
/* Interrupt disable mask for UFSHCI v1.0 */
|
|
||||||
INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
|
|
||||||
INTERRUPT_MASK_RW_VER_10 = 0x30000,
|
|
||||||
|
|
||||||
/* Interrupt disable mask for UFSHCI v1.1 */
|
|
||||||
INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
|
|
||||||
|
|
||||||
/* Interrupt disable mask for UFSHCI v2.1 */
|
|
||||||
INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* CCAP - Crypto Capability 100h */
|
|
||||||
union ufs_crypto_capabilities {
|
|
||||||
__le32 reg_val;
|
|
||||||
struct {
|
|
||||||
u8 num_crypto_cap;
|
|
||||||
u8 config_count;
|
|
||||||
u8 reserved;
|
|
||||||
u8 config_array_ptr;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_crypto_key_size {
|
|
||||||
UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
|
|
||||||
UFS_CRYPTO_KEY_SIZE_128 = 0x1,
|
|
||||||
UFS_CRYPTO_KEY_SIZE_192 = 0x2,
|
|
||||||
UFS_CRYPTO_KEY_SIZE_256 = 0x3,
|
|
||||||
UFS_CRYPTO_KEY_SIZE_512 = 0x4,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_crypto_alg {
|
|
||||||
UFS_CRYPTO_ALG_AES_XTS = 0x0,
|
|
||||||
UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
|
|
||||||
UFS_CRYPTO_ALG_AES_ECB = 0x2,
|
|
||||||
UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* x-CRYPTOCAP - Crypto Capability X */
|
|
||||||
union ufs_crypto_cap_entry {
|
|
||||||
__le32 reg_val;
|
|
||||||
struct {
|
|
||||||
u8 algorithm_id;
|
|
||||||
u8 sdus_mask; /* Supported data unit size mask */
|
|
||||||
u8 key_size;
|
|
||||||
u8 reserved;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
|
|
||||||
#define UFS_CRYPTO_KEY_MAX_SIZE 64
|
|
||||||
/* x-CRYPTOCFG - Crypto Configuration X */
|
|
||||||
union ufs_crypto_cfg_entry {
|
|
||||||
__le32 reg_val[32];
|
|
||||||
struct {
|
|
||||||
u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
|
|
||||||
u8 data_unit_size;
|
|
||||||
u8 crypto_cap_idx;
|
|
||||||
u8 reserved_1;
|
|
||||||
u8 config_enable;
|
|
||||||
u8 reserved_multi_host;
|
|
||||||
u8 reserved_2;
|
|
||||||
u8 vsb[2];
|
|
||||||
u8 reserved_3[56];
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Request Descriptor Definitions
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Transfer request command type */
|
|
||||||
enum {
|
|
||||||
UTP_CMD_TYPE_SCSI = 0x0,
|
|
||||||
UTP_CMD_TYPE_UFS = 0x1,
|
|
||||||
UTP_CMD_TYPE_DEV_MANAGE = 0x2,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* To accommodate UFS2.0 required Command type */
|
|
||||||
enum {
|
|
||||||
UTP_CMD_TYPE_UFS_STORAGE = 0x1,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum {
|
|
||||||
UTP_SCSI_COMMAND = 0x00000000,
|
|
||||||
UTP_NATIVE_UFS_COMMAND = 0x10000000,
|
|
||||||
UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
|
|
||||||
UTP_REQ_DESC_INT_CMD = 0x01000000,
|
|
||||||
UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP Transfer Request Data Direction (DD) */
|
|
||||||
enum {
|
|
||||||
UTP_NO_DATA_TRANSFER = 0x00000000,
|
|
||||||
UTP_HOST_TO_DEVICE = 0x02000000,
|
|
||||||
UTP_DEVICE_TO_HOST = 0x04000000,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Overall command status values */
|
|
||||||
enum {
|
|
||||||
OCS_SUCCESS = 0x0,
|
|
||||||
OCS_INVALID_CMD_TABLE_ATTR = 0x1,
|
|
||||||
OCS_INVALID_PRDT_ATTR = 0x2,
|
|
||||||
OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
|
|
||||||
OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
|
|
||||||
OCS_PEER_COMM_FAILURE = 0x5,
|
|
||||||
OCS_ABORTED = 0x6,
|
|
||||||
OCS_FATAL_ERROR = 0x7,
|
|
||||||
OCS_DEVICE_FATAL_ERROR = 0x8,
|
|
||||||
OCS_INVALID_CRYPTO_CONFIG = 0x9,
|
|
||||||
OCS_GENERAL_CRYPTO_ERROR = 0xA,
|
|
||||||
OCS_INVALID_COMMAND_STATUS = 0x0F,
|
|
||||||
MASK_OCS = 0x0F,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* The maximum length of the data byte count field in the PRDT is 256KB */
|
|
||||||
#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
|
|
||||||
/* The granularity of the data byte count field in the PRDT is 32-bit */
|
|
||||||
#define PRDT_DATA_BYTE_COUNT_PAD 4
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct ufshcd_sg_entry - UFSHCI PRD Entry
|
|
||||||
* @base_addr: Lower 32bit physical address DW-0
|
|
||||||
* @upper_addr: Upper 32bit physical address DW-1
|
|
||||||
* @reserved: Reserved for future use DW-2
|
|
||||||
* @size: size of physical segment DW-3
|
|
||||||
*/
|
|
||||||
struct ufshcd_sg_entry {
|
|
||||||
__le32 base_addr;
|
|
||||||
__le32 upper_addr;
|
|
||||||
__le32 reserved;
|
|
||||||
__le32 size;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_transfer_cmd_desc - UFS Command Descriptor structure
|
|
||||||
* @command_upiu: Command UPIU Frame address
|
|
||||||
* @response_upiu: Response UPIU Frame address
|
|
||||||
* @prd_table: Physical Region Descriptor
|
|
||||||
*/
|
|
||||||
struct utp_transfer_cmd_desc {
|
|
||||||
u8 command_upiu[ALIGNED_UPIU_SIZE];
|
|
||||||
u8 response_upiu[ALIGNED_UPIU_SIZE];
|
|
||||||
struct ufshcd_sg_entry prd_table[SG_ALL];
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
|
|
||||||
* @dword0: Descriptor Header DW0
|
|
||||||
* @dword1: Descriptor Header DW1
|
|
||||||
* @dword2: Descriptor Header DW2
|
|
||||||
* @dword3: Descriptor Header DW3
|
|
||||||
*/
|
|
||||||
struct request_desc_header {
|
|
||||||
__le32 dword_0;
|
|
||||||
__le32 dword_1;
|
|
||||||
__le32 dword_2;
|
|
||||||
__le32 dword_3;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_transfer_req_desc - UTRD structure
|
|
||||||
* @header: UTRD header DW-0 to DW-3
|
|
||||||
* @command_desc_base_addr_lo: UCD base address low DW-4
|
|
||||||
* @command_desc_base_addr_hi: UCD base address high DW-5
|
|
||||||
* @response_upiu_length: response UPIU length DW-6
|
|
||||||
* @response_upiu_offset: response UPIU offset DW-6
|
|
||||||
* @prd_table_length: Physical region descriptor length DW-7
|
|
||||||
* @prd_table_offset: Physical region descriptor offset DW-7
|
|
||||||
*/
|
|
||||||
struct utp_transfer_req_desc {
|
|
||||||
|
|
||||||
/* DW 0-3 */
|
|
||||||
struct request_desc_header header;
|
|
||||||
|
|
||||||
/* DW 4-5*/
|
|
||||||
__le32 command_desc_base_addr_lo;
|
|
||||||
__le32 command_desc_base_addr_hi;
|
|
||||||
|
|
||||||
/* DW 6 */
|
|
||||||
__le16 response_upiu_length;
|
|
||||||
__le16 response_upiu_offset;
|
|
||||||
|
|
||||||
/* DW 7 */
|
|
||||||
__le16 prd_table_length;
|
|
||||||
__le16 prd_table_offset;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* UTMRD structure.
|
|
||||||
*/
|
|
||||||
struct utp_task_req_desc {
|
|
||||||
/* DW 0-3 */
|
|
||||||
struct request_desc_header header;
|
|
||||||
|
|
||||||
/* DW 4-11 - Task request UPIU structure */
|
|
||||||
struct {
|
|
||||||
struct utp_upiu_header req_header;
|
|
||||||
__be32 input_param1;
|
|
||||||
__be32 input_param2;
|
|
||||||
__be32 input_param3;
|
|
||||||
__be32 __reserved1[2];
|
|
||||||
} upiu_req;
|
|
||||||
|
|
||||||
/* DW 12-19 - Task Management Response UPIU structure */
|
|
||||||
struct {
|
|
||||||
struct utp_upiu_header rsp_header;
|
|
||||||
__be32 output_param1;
|
|
||||||
__be32 output_param2;
|
|
||||||
__be32 __reserved2[3];
|
|
||||||
} upiu_rsp;
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* End of Header */
|
|
||||||
@@ -1,332 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
||||||
/*
|
|
||||||
* drivers/scsi/ufs/unipro.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _UNIPRO_H_
|
|
||||||
#define _UNIPRO_H_
|
|
||||||
|
|
||||||
/*
|
|
||||||
* M-TX Configuration Attributes
|
|
||||||
*/
|
|
||||||
#define TX_HIBERN8TIME_CAPABILITY 0x000F
|
|
||||||
#define TX_MODE 0x0021
|
|
||||||
#define TX_HSRATE_SERIES 0x0022
|
|
||||||
#define TX_HSGEAR 0x0023
|
|
||||||
#define TX_PWMGEAR 0x0024
|
|
||||||
#define TX_AMPLITUDE 0x0025
|
|
||||||
#define TX_HS_SLEWRATE 0x0026
|
|
||||||
#define TX_SYNC_SOURCE 0x0027
|
|
||||||
#define TX_HS_SYNC_LENGTH 0x0028
|
|
||||||
#define TX_HS_PREPARE_LENGTH 0x0029
|
|
||||||
#define TX_LS_PREPARE_LENGTH 0x002A
|
|
||||||
#define TX_HIBERN8_CONTROL 0x002B
|
|
||||||
#define TX_LCC_ENABLE 0x002C
|
|
||||||
#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D
|
|
||||||
#define TX_BYPASS_8B10B_ENABLE 0x002E
|
|
||||||
#define TX_DRIVER_POLARITY 0x002F
|
|
||||||
#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030
|
|
||||||
#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031
|
|
||||||
#define TX_LCC_SEQUENCER 0x0032
|
|
||||||
#define TX_MIN_ACTIVATETIME 0x0033
|
|
||||||
#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
|
|
||||||
#define TX_REFCLKFREQ 0x00EB
|
|
||||||
#define TX_CFGCLKFREQVAL 0x00EC
|
|
||||||
#define CFGEXTRATTR 0x00F0
|
|
||||||
#define DITHERCTRL2 0x00F1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* M-RX Configuration Attributes
|
|
||||||
*/
|
|
||||||
#define RX_MODE 0x00A1
|
|
||||||
#define RX_HSRATE_SERIES 0x00A2
|
|
||||||
#define RX_HSGEAR 0x00A3
|
|
||||||
#define RX_PWMGEAR 0x00A4
|
|
||||||
#define RX_LS_TERMINATED_ENABLE 0x00A5
|
|
||||||
#define RX_HS_UNTERMINATED_ENABLE 0x00A6
|
|
||||||
#define RX_ENTER_HIBERN8 0x00A7
|
|
||||||
#define RX_BYPASS_8B10B_ENABLE 0x00A8
|
|
||||||
#define RX_TERMINATION_FORCE_ENABLE 0x00A9
|
|
||||||
#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
|
|
||||||
#define RX_HIBERN8TIME_CAPABILITY 0x0092
|
|
||||||
#define RX_REFCLKFREQ 0x00EB
|
|
||||||
#define RX_CFGCLKFREQVAL 0x00EC
|
|
||||||
#define CFGWIDEINLN 0x00F0
|
|
||||||
#define CFGRXCDR8 0x00BA
|
|
||||||
#define ENARXDIRECTCFG4 0x00F2
|
|
||||||
#define CFGRXOVR8 0x00BD
|
|
||||||
#define RXDIRECTCTRL2 0x00C7
|
|
||||||
#define ENARXDIRECTCFG3 0x00F3
|
|
||||||
#define RXCALCTRL 0x00B4
|
|
||||||
#define ENARXDIRECTCFG2 0x00F4
|
|
||||||
#define CFGRXOVR4 0x00E9
|
|
||||||
#define RXSQCTRL 0x00B5
|
|
||||||
#define CFGRXOVR6 0x00BF
|
|
||||||
#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B
|
|
||||||
#define RX_HS_G1_PREP_LENGTH_CAP 0x008C
|
|
||||||
#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094
|
|
||||||
#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095
|
|
||||||
#define RX_HS_G2_PREP_LENGTH_CAP 0x0096
|
|
||||||
#define RX_HS_G3_PREP_LENGTH_CAP 0x0097
|
|
||||||
#define RX_ADV_GRANULARITY_CAP 0x0098
|
|
||||||
#define RX_MIN_ACTIVATETIME_CAP 0x008F
|
|
||||||
#define RX_HIBERN8TIME_CAP 0x0092
|
|
||||||
#define RX_ADV_HIBERN8TIME_CAP 0x0099
|
|
||||||
#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A
|
|
||||||
|
|
||||||
|
|
||||||
#define is_mphy_tx_attr(attr) (attr < RX_MODE)
|
|
||||||
#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
|
|
||||||
#define SYNC_LEN_FINE(x) ((x) & 0x3F)
|
|
||||||
#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F))
|
|
||||||
#define PREP_LEN(x) ((x) & 0xF)
|
|
||||||
|
|
||||||
#define RX_MIN_ACTIVATETIME_UNIT_US 100
|
|
||||||
#define HIBERN8TIME_UNIT_US 100
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Common Block Attributes
|
|
||||||
*/
|
|
||||||
#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B)
|
|
||||||
#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF)
|
|
||||||
#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD)
|
|
||||||
#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6)
|
|
||||||
#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA)
|
|
||||||
#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0)
|
|
||||||
#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1)
|
|
||||||
#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3)
|
|
||||||
#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
|
|
||||||
#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
|
|
||||||
|
|
||||||
#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PHY Adpater attributes
|
|
||||||
*/
|
|
||||||
#define PA_ACTIVETXDATALANES 0x1560
|
|
||||||
#define PA_ACTIVERXDATALANES 0x1580
|
|
||||||
#define PA_TXTRAILINGCLOCKS 0x1564
|
|
||||||
#define PA_PHY_TYPE 0x1500
|
|
||||||
#define PA_AVAILTXDATALANES 0x1520
|
|
||||||
#define PA_AVAILRXDATALANES 0x1540
|
|
||||||
#define PA_MINRXTRAILINGCLOCKS 0x1543
|
|
||||||
#define PA_TXPWRSTATUS 0x1567
|
|
||||||
#define PA_RXPWRSTATUS 0x1582
|
|
||||||
#define PA_TXFORCECLOCK 0x1562
|
|
||||||
#define PA_TXPWRMODE 0x1563
|
|
||||||
#define PA_LEGACYDPHYESCDL 0x1570
|
|
||||||
#define PA_MAXTXSPEEDFAST 0x1521
|
|
||||||
#define PA_MAXTXSPEEDSLOW 0x1522
|
|
||||||
#define PA_MAXRXSPEEDFAST 0x1541
|
|
||||||
#define PA_MAXRXSPEEDSLOW 0x1542
|
|
||||||
#define PA_TXLINKSTARTUPHS 0x1544
|
|
||||||
#define PA_LOCAL_TX_LCC_ENABLE 0x155E
|
|
||||||
#define PA_TXSPEEDFAST 0x1565
|
|
||||||
#define PA_TXSPEEDSLOW 0x1566
|
|
||||||
#define PA_REMOTEVERINFO 0x15A0
|
|
||||||
#define PA_TXGEAR 0x1568
|
|
||||||
#define PA_TXTERMINATION 0x1569
|
|
||||||
#define PA_HSSERIES 0x156A
|
|
||||||
#define PA_PWRMODE 0x1571
|
|
||||||
#define PA_RXGEAR 0x1583
|
|
||||||
#define PA_RXTERMINATION 0x1584
|
|
||||||
#define PA_MAXRXPWMGEAR 0x1586
|
|
||||||
#define PA_MAXRXHSGEAR 0x1587
|
|
||||||
#define PA_RXHSUNTERMCAP 0x15A5
|
|
||||||
#define PA_RXLSTERMCAP 0x15A6
|
|
||||||
#define PA_GRANULARITY 0x15AA
|
|
||||||
#define PA_PACPREQTIMEOUT 0x1590
|
|
||||||
#define PA_PACPREQEOBTIMEOUT 0x1591
|
|
||||||
#define PA_HIBERN8TIME 0x15A7
|
|
||||||
#define PA_LOCALVERINFO 0x15A9
|
|
||||||
#define PA_GRANULARITY 0x15AA
|
|
||||||
#define PA_TACTIVATE 0x15A8
|
|
||||||
#define PA_PACPFRAMECOUNT 0x15C0
|
|
||||||
#define PA_PACPERRORCOUNT 0x15C1
|
|
||||||
#define PA_PHYTESTCONTROL 0x15C2
|
|
||||||
#define PA_PWRMODEUSERDATA0 0x15B0
|
|
||||||
#define PA_PWRMODEUSERDATA1 0x15B1
|
|
||||||
#define PA_PWRMODEUSERDATA2 0x15B2
|
|
||||||
#define PA_PWRMODEUSERDATA3 0x15B3
|
|
||||||
#define PA_PWRMODEUSERDATA4 0x15B4
|
|
||||||
#define PA_PWRMODEUSERDATA5 0x15B5
|
|
||||||
#define PA_PWRMODEUSERDATA6 0x15B6
|
|
||||||
#define PA_PWRMODEUSERDATA7 0x15B7
|
|
||||||
#define PA_PWRMODEUSERDATA8 0x15B8
|
|
||||||
#define PA_PWRMODEUSERDATA9 0x15B9
|
|
||||||
#define PA_PWRMODEUSERDATA10 0x15BA
|
|
||||||
#define PA_PWRMODEUSERDATA11 0x15BB
|
|
||||||
#define PA_CONNECTEDTXDATALANES 0x1561
|
|
||||||
#define PA_CONNECTEDRXDATALANES 0x1581
|
|
||||||
#define PA_LOGICALLANEMAP 0x15A1
|
|
||||||
#define PA_SLEEPNOCONFIGTIME 0x15A2
|
|
||||||
#define PA_STALLNOCONFIGTIME 0x15A3
|
|
||||||
#define PA_SAVECONFIGTIME 0x15A4
|
|
||||||
#define PA_TXHSADAPTTYPE 0x15D4
|
|
||||||
|
|
||||||
/* Adpat type for PA_TXHSADAPTTYPE attribute */
|
|
||||||
#define PA_REFRESH_ADAPT 0x00
|
|
||||||
#define PA_INITIAL_ADAPT 0x01
|
|
||||||
#define PA_NO_ADAPT 0x03
|
|
||||||
|
|
||||||
#define PA_TACTIVATE_TIME_UNIT_US 10
|
|
||||||
#define PA_HIBERN8_TIME_UNIT_US 100
|
|
||||||
|
|
||||||
/*Other attributes*/
|
|
||||||
#define VS_MPHYCFGUPDT 0xD085
|
|
||||||
#define VS_DEBUGOMC 0xD09E
|
|
||||||
#define VS_POWERSTATE 0xD083
|
|
||||||
|
|
||||||
#define PA_GRANULARITY_MIN_VAL 1
|
|
||||||
#define PA_GRANULARITY_MAX_VAL 6
|
|
||||||
|
|
||||||
/* PHY Adapter Protocol Constants */
|
|
||||||
#define PA_MAXDATALANES 4
|
|
||||||
|
|
||||||
#define DL_FC0ProtectionTimeOutVal_Default 8191
|
|
||||||
#define DL_TC0ReplayTimeOutVal_Default 65535
|
|
||||||
#define DL_AFC0ReqTimeOutVal_Default 32767
|
|
||||||
#define DL_FC1ProtectionTimeOutVal_Default 8191
|
|
||||||
#define DL_TC1ReplayTimeOutVal_Default 65535
|
|
||||||
#define DL_AFC1ReqTimeOutVal_Default 32767
|
|
||||||
|
|
||||||
#define DME_LocalFC0ProtectionTimeOutVal 0xD041
|
|
||||||
#define DME_LocalTC0ReplayTimeOutVal 0xD042
|
|
||||||
#define DME_LocalAFC0ReqTimeOutVal 0xD043
|
|
||||||
|
|
||||||
/* PA power modes */
|
|
||||||
enum {
|
|
||||||
FAST_MODE = 1,
|
|
||||||
SLOW_MODE = 2,
|
|
||||||
FASTAUTO_MODE = 4,
|
|
||||||
SLOWAUTO_MODE = 5,
|
|
||||||
UNCHANGED = 7,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define PWRMODE_MASK 0xF
|
|
||||||
#define PWRMODE_RX_OFFSET 4
|
|
||||||
|
|
||||||
/* PA TX/RX Frequency Series */
|
|
||||||
enum {
|
|
||||||
PA_HS_MODE_A = 1,
|
|
||||||
PA_HS_MODE_B = 2,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_pwm_gear_tag {
|
|
||||||
UFS_PWM_DONT_CHANGE, /* Don't change Gear */
|
|
||||||
UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
|
|
||||||
UFS_PWM_G2, /* PWM Gear 2 */
|
|
||||||
UFS_PWM_G3, /* PWM Gear 3 */
|
|
||||||
UFS_PWM_G4, /* PWM Gear 4 */
|
|
||||||
UFS_PWM_G5, /* PWM Gear 5 */
|
|
||||||
UFS_PWM_G6, /* PWM Gear 6 */
|
|
||||||
UFS_PWM_G7, /* PWM Gear 7 */
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_hs_gear_tag {
|
|
||||||
UFS_HS_DONT_CHANGE, /* Don't change Gear */
|
|
||||||
UFS_HS_G1, /* HS Gear 1 (default for reset) */
|
|
||||||
UFS_HS_G2, /* HS Gear 2 */
|
|
||||||
UFS_HS_G3, /* HS Gear 3 */
|
|
||||||
UFS_HS_G4, /* HS Gear 4 */
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_unipro_ver {
|
|
||||||
UFS_UNIPRO_VER_RESERVED = 0,
|
|
||||||
UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
|
|
||||||
UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
|
|
||||||
UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
|
|
||||||
UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */
|
|
||||||
UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */
|
|
||||||
UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */
|
|
||||||
/* UniPro version field mask in PA_LOCALVERINFO */
|
|
||||||
UFS_UNIPRO_VER_MASK = 0xF,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Data Link Layer Attributes
|
|
||||||
*/
|
|
||||||
#define DL_TC0TXFCTHRESHOLD 0x2040
|
|
||||||
#define DL_FC0PROTTIMEOUTVAL 0x2041
|
|
||||||
#define DL_TC0REPLAYTIMEOUTVAL 0x2042
|
|
||||||
#define DL_AFC0REQTIMEOUTVAL 0x2043
|
|
||||||
#define DL_AFC0CREDITTHRESHOLD 0x2044
|
|
||||||
#define DL_TC0OUTACKTHRESHOLD 0x2045
|
|
||||||
#define DL_TC1TXFCTHRESHOLD 0x2060
|
|
||||||
#define DL_FC1PROTTIMEOUTVAL 0x2061
|
|
||||||
#define DL_TC1REPLAYTIMEOUTVAL 0x2062
|
|
||||||
#define DL_AFC1REQTIMEOUTVAL 0x2063
|
|
||||||
#define DL_AFC1CREDITTHRESHOLD 0x2064
|
|
||||||
#define DL_TC1OUTACKTHRESHOLD 0x2065
|
|
||||||
#define DL_TXPREEMPTIONCAP 0x2000
|
|
||||||
#define DL_TC0TXMAXSDUSIZE 0x2001
|
|
||||||
#define DL_TC0RXINITCREDITVAL 0x2002
|
|
||||||
#define DL_TC0TXBUFFERSIZE 0x2005
|
|
||||||
#define DL_PEERTC0PRESENT 0x2046
|
|
||||||
#define DL_PEERTC0RXINITCREVAL 0x2047
|
|
||||||
#define DL_TC1TXMAXSDUSIZE 0x2003
|
|
||||||
#define DL_TC1RXINITCREDITVAL 0x2004
|
|
||||||
#define DL_TC1TXBUFFERSIZE 0x2006
|
|
||||||
#define DL_PEERTC1PRESENT 0x2066
|
|
||||||
#define DL_PEERTC1RXINITCREVAL 0x2067
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Network Layer Attributes
|
|
||||||
*/
|
|
||||||
#define N_DEVICEID 0x3000
|
|
||||||
#define N_DEVICEID_VALID 0x3001
|
|
||||||
#define N_TC0TXMAXSDUSIZE 0x3020
|
|
||||||
#define N_TC1TXMAXSDUSIZE 0x3021
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Transport Layer Attributes
|
|
||||||
*/
|
|
||||||
#define T_NUMCPORTS 0x4000
|
|
||||||
#define T_NUMTESTFEATURES 0x4001
|
|
||||||
#define T_CONNECTIONSTATE 0x4020
|
|
||||||
#define T_PEERDEVICEID 0x4021
|
|
||||||
#define T_PEERCPORTID 0x4022
|
|
||||||
#define T_TRAFFICCLASS 0x4023
|
|
||||||
#define T_PROTOCOLID 0x4024
|
|
||||||
#define T_CPORTFLAGS 0x4025
|
|
||||||
#define T_TXTOKENVALUE 0x4026
|
|
||||||
#define T_RXTOKENVALUE 0x4027
|
|
||||||
#define T_LOCALBUFFERSPACE 0x4028
|
|
||||||
#define T_PEERBUFFERSPACE 0x4029
|
|
||||||
#define T_CREDITSTOSEND 0x402A
|
|
||||||
#define T_CPORTMODE 0x402B
|
|
||||||
#define T_TC0TXMAXSDUSIZE 0x4060
|
|
||||||
#define T_TC1TXMAXSDUSIZE 0x4061
|
|
||||||
|
|
||||||
#ifdef FALSE
|
|
||||||
#undef FALSE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef TRUE
|
|
||||||
#undef TRUE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Boolean attribute values */
|
|
||||||
enum {
|
|
||||||
FALSE = 0,
|
|
||||||
TRUE,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* CPort setting */
|
|
||||||
#define E2EFC_ON (1 << 0)
|
|
||||||
#define E2EFC_OFF (0 << 0)
|
|
||||||
#define CSD_N_ON (0 << 1)
|
|
||||||
#define CSD_N_OFF (1 << 1)
|
|
||||||
#define CSV_N_ON (0 << 2)
|
|
||||||
#define CSV_N_OFF (1 << 2)
|
|
||||||
#define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF)
|
|
||||||
|
|
||||||
/* CPort connection state */
|
|
||||||
enum {
|
|
||||||
CPORT_IDLE = 0,
|
|
||||||
CPORT_CONNECTED,
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* _UNIPRO_H_ */
|
|
||||||
@@ -1,652 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
||||||
/*
|
|
||||||
* Universal Flash Storage Host controller driver
|
|
||||||
* Copyright (C) 2011-2013 Samsung India Software Operations
|
|
||||||
*
|
|
||||||
* Authors:
|
|
||||||
* Santosh Yaraganavi <santosh.sy@samsung.com>
|
|
||||||
* Vinayak Holikatti <h.vinayak@samsung.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _UFS_H
|
|
||||||
#define _UFS_H
|
|
||||||
|
|
||||||
#include <linux/mutex.h>
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <uapi/scsi/scsi_bsg_ufs.h>
|
|
||||||
|
|
||||||
#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
|
|
||||||
#define QUERY_DESC_MAX_SIZE 255
|
|
||||||
#define QUERY_DESC_MIN_SIZE 2
|
|
||||||
#define QUERY_DESC_HDR_SIZE 2
|
|
||||||
#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
|
|
||||||
(sizeof(struct utp_upiu_header)))
|
|
||||||
#define UFS_SENSE_SIZE 18
|
|
||||||
|
|
||||||
#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
|
|
||||||
cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
|
|
||||||
(byte1 << 8) | (byte0))
|
|
||||||
/*
|
|
||||||
* UFS device may have standard LUs and LUN id could be from 0x00 to
|
|
||||||
* 0x7F. Standard LUs use "Peripheral Device Addressing Format".
|
|
||||||
* UFS device may also have the Well Known LUs (also referred as W-LU)
|
|
||||||
* which again could be from 0x00 to 0x7F. For W-LUs, device only use
|
|
||||||
* the "Extended Addressing Format" which means the W-LUNs would be
|
|
||||||
* from 0xc100 (SCSI_W_LUN_BASE) onwards.
|
|
||||||
* This means max. LUN number reported from UFS device could be 0xC17F.
|
|
||||||
*/
|
|
||||||
#define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
|
|
||||||
#define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
|
|
||||||
#define UFS_UPIU_WLUN_ID (1 << 7)
|
|
||||||
#define UFS_RPMB_UNIT 0xC4
|
|
||||||
|
|
||||||
/* WriteBooster buffer is available only for the logical unit from 0 to 7 */
|
|
||||||
#define UFS_UPIU_MAX_WB_LUN_ID 8
|
|
||||||
|
|
||||||
/* Well known logical unit id in LUN field of UPIU */
|
|
||||||
enum {
|
|
||||||
UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
|
|
||||||
UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
|
|
||||||
UFS_UPIU_BOOT_WLUN = 0xB0,
|
|
||||||
UFS_UPIU_RPMB_WLUN = 0xC4,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* UFS Protocol Information Unit related definitions
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Task management functions */
|
|
||||||
enum {
|
|
||||||
UFS_ABORT_TASK = 0x01,
|
|
||||||
UFS_ABORT_TASK_SET = 0x02,
|
|
||||||
UFS_CLEAR_TASK_SET = 0x04,
|
|
||||||
UFS_LOGICAL_RESET = 0x08,
|
|
||||||
UFS_QUERY_TASK = 0x80,
|
|
||||||
UFS_QUERY_TASK_SET = 0x81,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP UPIU Transaction Codes Initiator to Target */
|
|
||||||
enum {
|
|
||||||
UPIU_TRANSACTION_NOP_OUT = 0x00,
|
|
||||||
UPIU_TRANSACTION_COMMAND = 0x01,
|
|
||||||
UPIU_TRANSACTION_DATA_OUT = 0x02,
|
|
||||||
UPIU_TRANSACTION_TASK_REQ = 0x04,
|
|
||||||
UPIU_TRANSACTION_QUERY_REQ = 0x16,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP UPIU Transaction Codes Target to Initiator */
|
|
||||||
enum {
|
|
||||||
UPIU_TRANSACTION_NOP_IN = 0x20,
|
|
||||||
UPIU_TRANSACTION_RESPONSE = 0x21,
|
|
||||||
UPIU_TRANSACTION_DATA_IN = 0x22,
|
|
||||||
UPIU_TRANSACTION_TASK_RSP = 0x24,
|
|
||||||
UPIU_TRANSACTION_READY_XFER = 0x31,
|
|
||||||
UPIU_TRANSACTION_QUERY_RSP = 0x36,
|
|
||||||
UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UPIU Read/Write flags */
|
|
||||||
enum {
|
|
||||||
UPIU_CMD_FLAGS_NONE = 0x00,
|
|
||||||
UPIU_CMD_FLAGS_WRITE = 0x20,
|
|
||||||
UPIU_CMD_FLAGS_READ = 0x40,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UPIU Task Attributes */
|
|
||||||
enum {
|
|
||||||
UPIU_TASK_ATTR_SIMPLE = 0x00,
|
|
||||||
UPIU_TASK_ATTR_ORDERED = 0x01,
|
|
||||||
UPIU_TASK_ATTR_HEADQ = 0x02,
|
|
||||||
UPIU_TASK_ATTR_ACA = 0x03,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UPIU Query request function */
|
|
||||||
enum {
|
|
||||||
UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
|
|
||||||
UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Flag idn for Query Requests*/
|
|
||||||
enum flag_idn {
|
|
||||||
QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
|
|
||||||
QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
|
|
||||||
QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
|
|
||||||
QUERY_FLAG_IDN_BKOPS_EN = 0x04,
|
|
||||||
QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
|
|
||||||
QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
|
|
||||||
QUERY_FLAG_IDN_RESERVED2 = 0x07,
|
|
||||||
QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
|
|
||||||
QUERY_FLAG_IDN_BUSY_RTC = 0x09,
|
|
||||||
QUERY_FLAG_IDN_RESERVED3 = 0x0A,
|
|
||||||
QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
|
|
||||||
QUERY_FLAG_IDN_WB_EN = 0x0E,
|
|
||||||
QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
|
|
||||||
QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
|
|
||||||
QUERY_FLAG_IDN_HPB_RESET = 0x11,
|
|
||||||
QUERY_FLAG_IDN_HPB_EN = 0x12,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Attribute idn for Query requests */
|
|
||||||
enum attr_idn {
|
|
||||||
QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
|
|
||||||
QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
|
|
||||||
QUERY_ATTR_IDN_POWER_MODE = 0x02,
|
|
||||||
QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
|
|
||||||
QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
|
|
||||||
QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
|
|
||||||
QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
|
|
||||||
QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
|
|
||||||
QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
|
|
||||||
QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
|
|
||||||
QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
|
|
||||||
QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
|
|
||||||
QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
|
|
||||||
QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
|
|
||||||
QUERY_ATTR_IDN_EE_STATUS = 0x0E,
|
|
||||||
QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
|
|
||||||
QUERY_ATTR_IDN_CNTX_CONF = 0x10,
|
|
||||||
QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
|
|
||||||
QUERY_ATTR_IDN_RESERVED2 = 0x12,
|
|
||||||
QUERY_ATTR_IDN_RESERVED3 = 0x13,
|
|
||||||
QUERY_ATTR_IDN_FFU_STATUS = 0x14,
|
|
||||||
QUERY_ATTR_IDN_PSA_STATE = 0x15,
|
|
||||||
QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
|
|
||||||
QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
|
|
||||||
QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18,
|
|
||||||
QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19,
|
|
||||||
QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A,
|
|
||||||
QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
|
|
||||||
QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
|
|
||||||
QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
|
|
||||||
QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Descriptor idn for Query requests */
|
|
||||||
enum desc_idn {
|
|
||||||
QUERY_DESC_IDN_DEVICE = 0x0,
|
|
||||||
QUERY_DESC_IDN_CONFIGURATION = 0x1,
|
|
||||||
QUERY_DESC_IDN_UNIT = 0x2,
|
|
||||||
QUERY_DESC_IDN_RFU_0 = 0x3,
|
|
||||||
QUERY_DESC_IDN_INTERCONNECT = 0x4,
|
|
||||||
QUERY_DESC_IDN_STRING = 0x5,
|
|
||||||
QUERY_DESC_IDN_RFU_1 = 0x6,
|
|
||||||
QUERY_DESC_IDN_GEOMETRY = 0x7,
|
|
||||||
QUERY_DESC_IDN_POWER = 0x8,
|
|
||||||
QUERY_DESC_IDN_HEALTH = 0x9,
|
|
||||||
QUERY_DESC_IDN_MAX,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum desc_header_offset {
|
|
||||||
QUERY_DESC_LENGTH_OFFSET = 0x00,
|
|
||||||
QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Unit descriptor parameters offsets in bytes*/
|
|
||||||
enum unit_desc_param {
|
|
||||||
UNIT_DESC_PARAM_LEN = 0x0,
|
|
||||||
UNIT_DESC_PARAM_TYPE = 0x1,
|
|
||||||
UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
|
|
||||||
UNIT_DESC_PARAM_LU_ENABLE = 0x3,
|
|
||||||
UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
|
|
||||||
UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
|
|
||||||
UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
|
|
||||||
UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
|
|
||||||
UNIT_DESC_PARAM_MEM_TYPE = 0x8,
|
|
||||||
UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
|
|
||||||
UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
|
|
||||||
UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
|
|
||||||
UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
|
|
||||||
UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
|
|
||||||
UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
|
|
||||||
UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
|
|
||||||
UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
|
|
||||||
UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
|
|
||||||
UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
|
|
||||||
UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
|
|
||||||
UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Device descriptor parameters offsets in bytes*/
|
|
||||||
enum device_desc_param {
|
|
||||||
DEVICE_DESC_PARAM_LEN = 0x0,
|
|
||||||
DEVICE_DESC_PARAM_TYPE = 0x1,
|
|
||||||
DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
|
|
||||||
DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
|
|
||||||
DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
|
|
||||||
DEVICE_DESC_PARAM_PRTCL = 0x5,
|
|
||||||
DEVICE_DESC_PARAM_NUM_LU = 0x6,
|
|
||||||
DEVICE_DESC_PARAM_NUM_WLU = 0x7,
|
|
||||||
DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
|
|
||||||
DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
|
|
||||||
DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
|
|
||||||
DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
|
|
||||||
DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
|
|
||||||
DEVICE_DESC_PARAM_SEC_LU = 0xD,
|
|
||||||
DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
|
|
||||||
DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
|
|
||||||
DEVICE_DESC_PARAM_SPEC_VER = 0x10,
|
|
||||||
DEVICE_DESC_PARAM_MANF_DATE = 0x12,
|
|
||||||
DEVICE_DESC_PARAM_MANF_NAME = 0x14,
|
|
||||||
DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
|
|
||||||
DEVICE_DESC_PARAM_SN = 0x16,
|
|
||||||
DEVICE_DESC_PARAM_OEM_ID = 0x17,
|
|
||||||
DEVICE_DESC_PARAM_MANF_ID = 0x18,
|
|
||||||
DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
|
|
||||||
DEVICE_DESC_PARAM_UD_LEN = 0x1B,
|
|
||||||
DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
|
|
||||||
DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
|
|
||||||
DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
|
|
||||||
DEVICE_DESC_PARAM_FFU_TMT = 0x20,
|
|
||||||
DEVICE_DESC_PARAM_Q_DPTH = 0x21,
|
|
||||||
DEVICE_DESC_PARAM_DEV_VER = 0x22,
|
|
||||||
DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
|
|
||||||
DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
|
|
||||||
DEVICE_DESC_PARAM_PSA_TMT = 0x29,
|
|
||||||
DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
|
|
||||||
DEVICE_DESC_PARAM_HPB_VER = 0x40,
|
|
||||||
DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
|
|
||||||
DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
|
|
||||||
DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
|
|
||||||
DEVICE_DESC_PARAM_WB_TYPE = 0x54,
|
|
||||||
DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Interconnect descriptor parameters offsets in bytes*/
|
|
||||||
enum interconnect_desc_param {
|
|
||||||
INTERCONNECT_DESC_PARAM_LEN = 0x0,
|
|
||||||
INTERCONNECT_DESC_PARAM_TYPE = 0x1,
|
|
||||||
INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
|
|
||||||
INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Geometry descriptor parameters offsets in bytes*/
|
|
||||||
enum geometry_desc_param {
|
|
||||||
GEOMETRY_DESC_PARAM_LEN = 0x0,
|
|
||||||
GEOMETRY_DESC_PARAM_TYPE = 0x1,
|
|
||||||
GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
|
|
||||||
GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
|
|
||||||
GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
|
|
||||||
GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
|
|
||||||
GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
|
|
||||||
GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
|
|
||||||
GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
|
|
||||||
GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
|
|
||||||
GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
|
|
||||||
GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
|
|
||||||
GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
|
|
||||||
GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
|
|
||||||
GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
|
|
||||||
GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
|
|
||||||
GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
|
|
||||||
GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
|
|
||||||
GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
|
|
||||||
GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
|
|
||||||
GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
|
|
||||||
GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
|
|
||||||
GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
|
|
||||||
GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
|
|
||||||
GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
|
|
||||||
GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
|
|
||||||
GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
|
|
||||||
GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
|
|
||||||
GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
|
|
||||||
GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Health descriptor parameters offsets in bytes*/
|
|
||||||
enum health_desc_param {
|
|
||||||
HEALTH_DESC_PARAM_LEN = 0x0,
|
|
||||||
HEALTH_DESC_PARAM_TYPE = 0x1,
|
|
||||||
HEALTH_DESC_PARAM_EOL_INFO = 0x2,
|
|
||||||
HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
|
|
||||||
HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* WriteBooster buffer mode */
|
|
||||||
enum {
|
|
||||||
WB_BUF_MODE_LU_DEDICATED = 0x0,
|
|
||||||
WB_BUF_MODE_SHARED = 0x1,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Logical Unit Write Protect
|
|
||||||
* 00h: LU not write protected
|
|
||||||
* 01h: LU write protected when fPowerOnWPEn =1
|
|
||||||
* 02h: LU permanently write protected when fPermanentWPEn =1
|
|
||||||
*/
|
|
||||||
enum ufs_lu_wp_type {
|
|
||||||
UFS_LU_NO_WP = 0x00,
|
|
||||||
UFS_LU_POWER_ON_WP = 0x01,
|
|
||||||
UFS_LU_PERM_WP = 0x02,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* bActiveICCLevel parameter current units */
|
|
||||||
enum {
|
|
||||||
UFSHCD_NANO_AMP = 0,
|
|
||||||
UFSHCD_MICRO_AMP = 1,
|
|
||||||
UFSHCD_MILI_AMP = 2,
|
|
||||||
UFSHCD_AMP = 3,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Possible values for dExtendedUFSFeaturesSupport */
|
|
||||||
enum {
|
|
||||||
UFS_DEV_LOW_TEMP_NOTIF = BIT(4),
|
|
||||||
UFS_DEV_HIGH_TEMP_NOTIF = BIT(5),
|
|
||||||
UFS_DEV_EXT_TEMP_NOTIF = BIT(6),
|
|
||||||
UFS_DEV_HPB_SUPPORT = BIT(7),
|
|
||||||
UFS_DEV_WRITE_BOOSTER_SUP = BIT(8),
|
|
||||||
};
|
|
||||||
#define UFS_DEV_HPB_SUPPORT_VERSION 0x310
|
|
||||||
|
|
||||||
#define POWER_DESC_MAX_ACTV_ICC_LVLS 16
|
|
||||||
|
|
||||||
/* Attribute bActiveICCLevel parameter bit masks definitions */
|
|
||||||
#define ATTR_ICC_LVL_UNIT_OFFSET 14
|
|
||||||
#define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
|
|
||||||
#define ATTR_ICC_LVL_VALUE_MASK 0x3FF
|
|
||||||
|
|
||||||
/* Power descriptor parameters offsets in bytes */
|
|
||||||
enum power_desc_param_offset {
|
|
||||||
PWR_DESC_LEN = 0x0,
|
|
||||||
PWR_DESC_TYPE = 0x1,
|
|
||||||
PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2,
|
|
||||||
PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22,
|
|
||||||
PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Exception event mask values */
|
|
||||||
enum {
|
|
||||||
MASK_EE_STATUS = 0xFFFF,
|
|
||||||
MASK_EE_DYNCAP_EVENT = BIT(0),
|
|
||||||
MASK_EE_SYSPOOL_EVENT = BIT(1),
|
|
||||||
MASK_EE_URGENT_BKOPS = BIT(2),
|
|
||||||
MASK_EE_TOO_HIGH_TEMP = BIT(3),
|
|
||||||
MASK_EE_TOO_LOW_TEMP = BIT(4),
|
|
||||||
MASK_EE_WRITEBOOSTER_EVENT = BIT(5),
|
|
||||||
MASK_EE_PERFORMANCE_THROTTLING = BIT(6),
|
|
||||||
};
|
|
||||||
#define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP)
|
|
||||||
|
|
||||||
/* Background operation status */
|
|
||||||
enum bkops_status {
|
|
||||||
BKOPS_STATUS_NO_OP = 0x0,
|
|
||||||
BKOPS_STATUS_NON_CRITICAL = 0x1,
|
|
||||||
BKOPS_STATUS_PERF_IMPACT = 0x2,
|
|
||||||
BKOPS_STATUS_CRITICAL = 0x3,
|
|
||||||
BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP QUERY Transaction Specific Fields OpCode */
|
|
||||||
enum query_opcode {
|
|
||||||
UPIU_QUERY_OPCODE_NOP = 0x0,
|
|
||||||
UPIU_QUERY_OPCODE_READ_DESC = 0x1,
|
|
||||||
UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
|
|
||||||
UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
|
|
||||||
UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
|
|
||||||
UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
|
|
||||||
UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
|
|
||||||
UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
|
|
||||||
UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* bRefClkFreq attribute values */
|
|
||||||
enum ufs_ref_clk_freq {
|
|
||||||
REF_CLK_FREQ_19_2_MHZ = 0,
|
|
||||||
REF_CLK_FREQ_26_MHZ = 1,
|
|
||||||
REF_CLK_FREQ_38_4_MHZ = 2,
|
|
||||||
REF_CLK_FREQ_52_MHZ = 3,
|
|
||||||
REF_CLK_FREQ_INVAL = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ufs_ref_clk {
|
|
||||||
unsigned long freq_hz;
|
|
||||||
enum ufs_ref_clk_freq val;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Query response result code */
|
|
||||||
enum {
|
|
||||||
QUERY_RESULT_SUCCESS = 0x00,
|
|
||||||
QUERY_RESULT_NOT_READABLE = 0xF6,
|
|
||||||
QUERY_RESULT_NOT_WRITEABLE = 0xF7,
|
|
||||||
QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
|
|
||||||
QUERY_RESULT_INVALID_LENGTH = 0xF9,
|
|
||||||
QUERY_RESULT_INVALID_VALUE = 0xFA,
|
|
||||||
QUERY_RESULT_INVALID_SELECTOR = 0xFB,
|
|
||||||
QUERY_RESULT_INVALID_INDEX = 0xFC,
|
|
||||||
QUERY_RESULT_INVALID_IDN = 0xFD,
|
|
||||||
QUERY_RESULT_INVALID_OPCODE = 0xFE,
|
|
||||||
QUERY_RESULT_GENERAL_FAILURE = 0xFF,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP Transfer Request Command Type (CT) */
|
|
||||||
enum {
|
|
||||||
UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
|
|
||||||
UPIU_COMMAND_SET_TYPE_UFS = 0x1,
|
|
||||||
UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP Transfer Request Command Offset */
|
|
||||||
#define UPIU_COMMAND_TYPE_OFFSET 28
|
|
||||||
|
|
||||||
/* Offset of the response code in the UPIU header */
|
|
||||||
#define UPIU_RSP_CODE_OFFSET 8
|
|
||||||
|
|
||||||
enum {
|
|
||||||
MASK_SCSI_STATUS = 0xFF,
|
|
||||||
MASK_TASK_RESPONSE = 0xFF00,
|
|
||||||
MASK_RSP_UPIU_RESULT = 0xFFFF,
|
|
||||||
MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
|
|
||||||
MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
|
|
||||||
MASK_RSP_EXCEPTION_EVENT = 0x10000,
|
|
||||||
MASK_TM_SERVICE_RESP = 0xFF,
|
|
||||||
MASK_TM_FUNC = 0xFF,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Task management service response */
|
|
||||||
enum {
|
|
||||||
UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
|
|
||||||
UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
|
|
||||||
UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
|
|
||||||
UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
|
|
||||||
UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UFS device power modes */
|
|
||||||
enum ufs_dev_pwr_mode {
|
|
||||||
UFS_ACTIVE_PWR_MODE = 1,
|
|
||||||
UFS_SLEEP_PWR_MODE = 2,
|
|
||||||
UFS_POWERDOWN_PWR_MODE = 3,
|
|
||||||
UFS_DEEPSLEEP_PWR_MODE = 4,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_cmd_rsp - Response UPIU structure
|
|
||||||
* @residual_transfer_count: Residual transfer count DW-3
|
|
||||||
* @reserved: Reserved double words DW-4 to DW-7
|
|
||||||
* @sense_data_len: Sense data length DW-8 U16
|
|
||||||
* @sense_data: Sense data field DW-8 to DW-12
|
|
||||||
*/
|
|
||||||
struct utp_cmd_rsp {
|
|
||||||
__be32 residual_transfer_count;
|
|
||||||
__be32 reserved[4];
|
|
||||||
__be16 sense_data_len;
|
|
||||||
u8 sense_data[UFS_SENSE_SIZE];
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ufshpb_active_field {
|
|
||||||
__be16 active_rgn;
|
|
||||||
__be16 active_srgn;
|
|
||||||
};
|
|
||||||
#define HPB_ACT_FIELD_SIZE 4
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_hpb_rsp - Response UPIU structure
|
|
||||||
* @residual_transfer_count: Residual transfer count DW-3
|
|
||||||
* @reserved1: Reserved double words DW-4 to DW-7
|
|
||||||
* @sense_data_len: Sense data length DW-8 U16
|
|
||||||
* @desc_type: Descriptor type of sense data
|
|
||||||
* @additional_len: Additional length of sense data
|
|
||||||
* @hpb_op: HPB operation type
|
|
||||||
* @lun: LUN of response UPIU
|
|
||||||
* @active_rgn_cnt: Active region count
|
|
||||||
* @inactive_rgn_cnt: Inactive region count
|
|
||||||
* @hpb_active_field: Recommended to read HPB region and subregion
|
|
||||||
* @hpb_inactive_field: To be inactivated HPB region and subregion
|
|
||||||
*/
|
|
||||||
struct utp_hpb_rsp {
|
|
||||||
__be32 residual_transfer_count;
|
|
||||||
__be32 reserved1[4];
|
|
||||||
__be16 sense_data_len;
|
|
||||||
u8 desc_type;
|
|
||||||
u8 additional_len;
|
|
||||||
u8 hpb_op;
|
|
||||||
u8 lun;
|
|
||||||
u8 active_rgn_cnt;
|
|
||||||
u8 inactive_rgn_cnt;
|
|
||||||
struct ufshpb_active_field hpb_active_field[2];
|
|
||||||
__be16 hpb_inactive_field[2];
|
|
||||||
};
|
|
||||||
#define UTP_HPB_RSP_SIZE 40
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_upiu_rsp - general upiu response structure
|
|
||||||
* @header: UPIU header structure DW-0 to DW-2
|
|
||||||
* @sr: fields structure for scsi command DW-3 to DW-12
|
|
||||||
* @qr: fields structure for query request DW-3 to DW-7
|
|
||||||
*/
|
|
||||||
struct utp_upiu_rsp {
|
|
||||||
struct utp_upiu_header header;
|
|
||||||
union {
|
|
||||||
struct utp_cmd_rsp sr;
|
|
||||||
struct utp_hpb_rsp hr;
|
|
||||||
struct utp_upiu_query qr;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct ufs_query_req - parameters for building a query request
|
|
||||||
* @query_func: UPIU header query function
|
|
||||||
* @upiu_req: the query request data
|
|
||||||
*/
|
|
||||||
struct ufs_query_req {
|
|
||||||
u8 query_func;
|
|
||||||
struct utp_upiu_query upiu_req;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct ufs_query_resp - UPIU QUERY
|
|
||||||
* @response: device response code
|
|
||||||
* @upiu_res: query response data
|
|
||||||
*/
|
|
||||||
struct ufs_query_res {
|
|
||||||
u8 response;
|
|
||||||
struct utp_upiu_query upiu_res;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define UFS_VREG_VCC_MIN_UV 2700000 /* uV */
|
|
||||||
#define UFS_VREG_VCC_MAX_UV 3600000 /* uV */
|
|
||||||
#define UFS_VREG_VCC_1P8_MIN_UV 1700000 /* uV */
|
|
||||||
#define UFS_VREG_VCC_1P8_MAX_UV 1950000 /* uV */
|
|
||||||
#define UFS_VREG_VCCQ_MIN_UV 1140000 /* uV */
|
|
||||||
#define UFS_VREG_VCCQ_MAX_UV 1260000 /* uV */
|
|
||||||
#define UFS_VREG_VCCQ2_MIN_UV 1700000 /* uV */
|
|
||||||
#define UFS_VREG_VCCQ2_MAX_UV 1950000 /* uV */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* VCCQ & VCCQ2 current requirement when UFS device is in sleep state
|
|
||||||
* and link is in Hibern8 state.
|
|
||||||
*/
|
|
||||||
#define UFS_VREG_LPM_LOAD_UA 1000 /* uA */
|
|
||||||
|
|
||||||
struct ufs_vreg {
|
|
||||||
struct regulator *reg;
|
|
||||||
const char *name;
|
|
||||||
bool always_on;
|
|
||||||
bool enabled;
|
|
||||||
int min_uV;
|
|
||||||
int max_uV;
|
|
||||||
int max_uA;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ufs_vreg_info {
|
|
||||||
struct ufs_vreg *vcc;
|
|
||||||
struct ufs_vreg *vccq;
|
|
||||||
struct ufs_vreg *vccq2;
|
|
||||||
struct ufs_vreg *vdd_hba;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ufs_dev_info {
|
|
||||||
bool f_power_on_wp_en;
|
|
||||||
/* Keeps information if any of the LU is power on write protected */
|
|
||||||
bool is_lu_power_on_wp;
|
|
||||||
/* Maximum number of general LU supported by the UFS device */
|
|
||||||
u8 max_lu_supported;
|
|
||||||
u16 wmanufacturerid;
|
|
||||||
/*UFS device Product Name */
|
|
||||||
u8 *model;
|
|
||||||
u16 wspecversion;
|
|
||||||
u32 clk_gating_wait_us;
|
|
||||||
|
|
||||||
/* UFS HPB related flag */
|
|
||||||
bool hpb_enabled;
|
|
||||||
|
|
||||||
/* UFS WB related flags */
|
|
||||||
bool wb_enabled;
|
|
||||||
bool wb_buf_flush_enabled;
|
|
||||||
u8 wb_dedicated_lu;
|
|
||||||
u8 wb_buffer_type;
|
|
||||||
|
|
||||||
bool b_rpm_dev_flush_capable;
|
|
||||||
u8 b_presrv_uspc_en;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This enum is used in string mapping in include/trace/events/ufs.h.
|
|
||||||
*/
|
|
||||||
enum ufs_trace_str_t {
|
|
||||||
UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP,
|
|
||||||
UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR,
|
|
||||||
UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Transaction Specific Fields (TSF) type in the UPIU package, this enum is
|
|
||||||
* used in include/trace/events/ufs.h for UFS command trace.
|
|
||||||
*/
|
|
||||||
enum ufs_trace_tsf_t {
|
|
||||||
UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* ufs_is_valid_unit_desc_lun - checks if the given LUN has a unit descriptor
|
|
||||||
* @dev_info: pointer of instance of struct ufs_dev_info
|
|
||||||
* @lun: LU number to check
|
|
||||||
* @return: true if the lun has a matching unit descriptor, false otherwise
|
|
||||||
*/
|
|
||||||
static inline bool ufs_is_valid_unit_desc_lun(struct ufs_dev_info *dev_info,
|
|
||||||
u8 lun, u8 param_offset)
|
|
||||||
{
|
|
||||||
if (!dev_info || !dev_info->max_lu_supported) {
|
|
||||||
pr_err("Max General LU supported by UFS isn't initialized\n");
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
/* WB is available only for the logical unit from 0 to 7 */
|
|
||||||
if (param_offset == UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS)
|
|
||||||
return lun < UFS_UPIU_MAX_WB_LUN_ID;
|
|
||||||
return lun == UFS_UPIU_RPMB_WLUN || (lun < dev_info->max_lu_supported);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* End of Header */
|
|
||||||
@@ -1,125 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
||||||
/*
|
|
||||||
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _UFS_QUIRKS_H_
|
|
||||||
#define _UFS_QUIRKS_H_
|
|
||||||
|
|
||||||
/* return true if s1 is a prefix of s2 */
|
|
||||||
#define STR_PRFX_EQUAL(s1, s2) !strncmp(s1, s2, strlen(s1))
|
|
||||||
|
|
||||||
#define UFS_ANY_VENDOR 0xFFFF
|
|
||||||
#define UFS_ANY_MODEL "ANY_MODEL"
|
|
||||||
|
|
||||||
#define UFS_VENDOR_MICRON 0x12C
|
|
||||||
#define UFS_VENDOR_SAMSUNG 0x1CE
|
|
||||||
#define UFS_VENDOR_SKHYNIX 0x1AD
|
|
||||||
#define UFS_VENDOR_TOSHIBA 0x198
|
|
||||||
#define UFS_VENDOR_WDC 0x145
|
|
||||||
|
|
||||||
/**
|
|
||||||
* ufs_dev_fix - ufs device quirk info
|
|
||||||
* @card: ufs card details
|
|
||||||
* @quirk: device quirk
|
|
||||||
*/
|
|
||||||
struct ufs_dev_fix {
|
|
||||||
u16 wmanufacturerid;
|
|
||||||
u8 *model;
|
|
||||||
unsigned int quirk;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define END_FIX { }
|
|
||||||
|
|
||||||
/* add specific device quirk */
|
|
||||||
#define UFS_FIX(_vendor, _model, _quirk) { \
|
|
||||||
.wmanufacturerid = (_vendor),\
|
|
||||||
.model = (_model), \
|
|
||||||
.quirk = (_quirk), \
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some vendor's UFS device sends back to back NACs for the DL data frames
|
|
||||||
* causing the host controller to raise the DFES error status. Sometimes
|
|
||||||
* such UFS devices send back to back NAC without waiting for new
|
|
||||||
* retransmitted DL frame from the host and in such cases it might be possible
|
|
||||||
* the Host UniPro goes into bad state without raising the DFES error
|
|
||||||
* interrupt. If this happens then all the pending commands would timeout
|
|
||||||
* only after respective SW command (which is generally too large).
|
|
||||||
*
|
|
||||||
* We can workaround such device behaviour like this:
|
|
||||||
* - As soon as SW sees the DL NAC error, it should schedule the error handler
|
|
||||||
* - Error handler would sleep for 50ms to see if there are any fatal errors
|
|
||||||
* raised by UFS controller.
|
|
||||||
* - If there are fatal errors then SW does normal error recovery.
|
|
||||||
* - If there are no fatal errors then SW sends the NOP command to device
|
|
||||||
* to check if link is alive.
|
|
||||||
* - If NOP command times out, SW does normal error recovery
|
|
||||||
* - If NOP command succeed, skip the error handling.
|
|
||||||
*
|
|
||||||
* If DL NAC error is seen multiple times with some vendor's UFS devices then
|
|
||||||
* enable this quirk to initiate quick error recovery and also silence related
|
|
||||||
* error logs to reduce spamming of kernel logs.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS (1 << 2)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Few Toshiba UFS device models advertise RX_MIN_ACTIVATETIME_CAPABILITY as
|
|
||||||
* 600us which may not be enough for reliable hibern8 exit hardware sequence
|
|
||||||
* from UFS device.
|
|
||||||
* To workaround this issue, host should set its PA_TACTIVATE time to 1ms even
|
|
||||||
* if device advertises RX_MIN_ACTIVATETIME_CAPABILITY less than 1ms.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_PA_TACTIVATE (1 << 4)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* It seems some UFS devices may keep drawing more than sleep current
|
|
||||||
* (atleast for 500us) from UFS rails (especially from VCCQ rail).
|
|
||||||
* To avoid this situation, add 2ms delay before putting these UFS
|
|
||||||
* rails in LPM mode.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM (1 << 6)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some UFS devices require host PA_TACTIVATE to be lower than device
|
|
||||||
* PA_TACTIVATE, enabling this quirk ensure this.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE (1 << 7)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The max. value PA_SaveConfigTime is 250 (10us) but this is not enough for
|
|
||||||
* some vendors.
|
|
||||||
* Gear switch from PWM to HS may fail even with this max. PA_SaveConfigTime.
|
|
||||||
* Gear switch can be issued by host controller as an error recovery and any
|
|
||||||
* software delay will not help on this case so we need to increase
|
|
||||||
* PA_SaveConfigTime to >32us as per vendor recommendation.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME (1 << 8)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some UFS devices require VS_DebugSaveConfigTime is 0x10,
|
|
||||||
* enabling this quirk ensure this.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME (1 << 9)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some pre-3.1 UFS devices can support extended features by upgrading
|
|
||||||
* the firmware. Enable this quirk to make UFS core driver probe and enable
|
|
||||||
* supported features on such devices.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES (1 << 10)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some UFS devices require delay after VCC power rail is turned-off.
|
|
||||||
* Enable this quirk to introduce 5ms delays after VCC power-off during
|
|
||||||
* suspend flow.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_DELAY_AFTER_LPM (1 << 11)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Some UFS devices require L2P entry should be swapped before being sent to the
|
|
||||||
* UFS device for HPB READ command.
|
|
||||||
*/
|
|
||||||
#define UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ (1 << 12)
|
|
||||||
|
|
||||||
#endif /* UFS_QUIRKS_H_ */
|
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -1,508 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
||||||
/*
|
|
||||||
* Universal Flash Storage Host controller driver
|
|
||||||
* Copyright (C) 2011-2013 Samsung India Software Operations
|
|
||||||
*
|
|
||||||
* Authors:
|
|
||||||
* Santosh Yaraganavi <santosh.sy@samsung.com>
|
|
||||||
* Vinayak Holikatti <h.vinayak@samsung.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _UFSHCI_H
|
|
||||||
#define _UFSHCI_H
|
|
||||||
|
|
||||||
enum {
|
|
||||||
TASK_REQ_UPIU_SIZE_DWORDS = 8,
|
|
||||||
TASK_RSP_UPIU_SIZE_DWORDS = 8,
|
|
||||||
ALIGNED_UPIU_SIZE = 512,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UFSHCI Registers */
|
|
||||||
enum {
|
|
||||||
REG_CONTROLLER_CAPABILITIES = 0x00,
|
|
||||||
REG_UFS_VERSION = 0x08,
|
|
||||||
REG_CONTROLLER_DEV_ID = 0x10,
|
|
||||||
REG_CONTROLLER_PROD_ID = 0x14,
|
|
||||||
REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
|
|
||||||
REG_INTERRUPT_STATUS = 0x20,
|
|
||||||
REG_INTERRUPT_ENABLE = 0x24,
|
|
||||||
REG_CONTROLLER_STATUS = 0x30,
|
|
||||||
REG_CONTROLLER_ENABLE = 0x34,
|
|
||||||
REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
|
|
||||||
REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
|
|
||||||
REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
|
|
||||||
REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
|
|
||||||
REG_UIC_ERROR_CODE_DME = 0x48,
|
|
||||||
REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
|
|
||||||
REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
|
|
||||||
REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
|
|
||||||
REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
|
|
||||||
REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
|
|
||||||
REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
|
|
||||||
REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
|
|
||||||
REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
|
|
||||||
REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
|
|
||||||
REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
|
|
||||||
REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
|
|
||||||
REG_UIC_COMMAND = 0x90,
|
|
||||||
REG_UIC_COMMAND_ARG_1 = 0x94,
|
|
||||||
REG_UIC_COMMAND_ARG_2 = 0x98,
|
|
||||||
REG_UIC_COMMAND_ARG_3 = 0x9C,
|
|
||||||
|
|
||||||
UFSHCI_REG_SPACE_SIZE = 0xA0,
|
|
||||||
|
|
||||||
REG_UFS_CCAP = 0x100,
|
|
||||||
REG_UFS_CRYPTOCAP = 0x104,
|
|
||||||
|
|
||||||
UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Controller capability masks */
|
|
||||||
enum {
|
|
||||||
MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
|
|
||||||
MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
|
|
||||||
MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
|
|
||||||
MASK_64_ADDRESSING_SUPPORT = 0x01000000,
|
|
||||||
MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
|
|
||||||
MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
|
|
||||||
MASK_CRYPTO_SUPPORT = 0x10000000,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define UFS_MASK(mask, offset) ((mask) << (offset))
|
|
||||||
|
|
||||||
/* UFS Version 08h */
|
|
||||||
#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
|
|
||||||
#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Controller UFSHCI version
|
|
||||||
* - 2.x and newer use the following scheme:
|
|
||||||
* major << 8 + minor << 4
|
|
||||||
* - 1.x has been converted to match this in
|
|
||||||
* ufshcd_get_ufs_version()
|
|
||||||
*/
|
|
||||||
static inline u32 ufshci_version(u32 major, u32 minor)
|
|
||||||
{
|
|
||||||
return (major << 8) + (minor << 4);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* HCDDID - Host Controller Identification Descriptor
|
|
||||||
* - Device ID and Device Class 10h
|
|
||||||
*/
|
|
||||||
#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
|
|
||||||
#define DEVICE_ID UFS_MASK(0xFF, 24)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* HCPMID - Host Controller Identification Descriptor
|
|
||||||
* - Product/Manufacturer ID 14h
|
|
||||||
*/
|
|
||||||
#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
|
|
||||||
#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
|
|
||||||
|
|
||||||
/* AHIT - Auto-Hibernate Idle Timer */
|
|
||||||
#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
|
|
||||||
#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
|
|
||||||
#define UFSHCI_AHIBERN8_SCALE_FACTOR 10
|
|
||||||
#define UFSHCI_AHIBERN8_MAX (1023 * 100000)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IS - Interrupt Status - 20h
|
|
||||||
*/
|
|
||||||
#define UTP_TRANSFER_REQ_COMPL 0x1
|
|
||||||
#define UIC_DME_END_PT_RESET 0x2
|
|
||||||
#define UIC_ERROR 0x4
|
|
||||||
#define UIC_TEST_MODE 0x8
|
|
||||||
#define UIC_POWER_MODE 0x10
|
|
||||||
#define UIC_HIBERNATE_EXIT 0x20
|
|
||||||
#define UIC_HIBERNATE_ENTER 0x40
|
|
||||||
#define UIC_LINK_LOST 0x80
|
|
||||||
#define UIC_LINK_STARTUP 0x100
|
|
||||||
#define UTP_TASK_REQ_COMPL 0x200
|
|
||||||
#define UIC_COMMAND_COMPL 0x400
|
|
||||||
#define DEVICE_FATAL_ERROR 0x800
|
|
||||||
#define CONTROLLER_FATAL_ERROR 0x10000
|
|
||||||
#define SYSTEM_BUS_FATAL_ERROR 0x20000
|
|
||||||
#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
|
|
||||||
|
|
||||||
#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
|
|
||||||
UIC_HIBERNATE_EXIT)
|
|
||||||
|
|
||||||
#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
|
|
||||||
UIC_POWER_MODE)
|
|
||||||
|
|
||||||
#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
|
|
||||||
|
|
||||||
#define UFSHCD_ERROR_MASK (UIC_ERROR |\
|
|
||||||
DEVICE_FATAL_ERROR |\
|
|
||||||
CONTROLLER_FATAL_ERROR |\
|
|
||||||
SYSTEM_BUS_FATAL_ERROR |\
|
|
||||||
CRYPTO_ENGINE_FATAL_ERROR)
|
|
||||||
|
|
||||||
#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
|
|
||||||
CONTROLLER_FATAL_ERROR |\
|
|
||||||
SYSTEM_BUS_FATAL_ERROR |\
|
|
||||||
CRYPTO_ENGINE_FATAL_ERROR |\
|
|
||||||
UIC_LINK_LOST)
|
|
||||||
|
|
||||||
/* HCS - Host Controller Status 30h */
|
|
||||||
#define DEVICE_PRESENT 0x1
|
|
||||||
#define UTP_TRANSFER_REQ_LIST_READY 0x2
|
|
||||||
#define UTP_TASK_REQ_LIST_READY 0x4
|
|
||||||
#define UIC_COMMAND_READY 0x8
|
|
||||||
#define HOST_ERROR_INDICATOR 0x10
|
|
||||||
#define DEVICE_ERROR_INDICATOR 0x20
|
|
||||||
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
|
|
||||||
|
|
||||||
#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
|
|
||||||
UTP_TASK_REQ_LIST_READY |\
|
|
||||||
UIC_COMMAND_READY)
|
|
||||||
|
|
||||||
enum {
|
|
||||||
PWR_OK = 0x0,
|
|
||||||
PWR_LOCAL = 0x01,
|
|
||||||
PWR_REMOTE = 0x02,
|
|
||||||
PWR_BUSY = 0x03,
|
|
||||||
PWR_ERROR_CAP = 0x04,
|
|
||||||
PWR_FATAL_ERROR = 0x05,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* HCE - Host Controller Enable 34h */
|
|
||||||
#define CONTROLLER_ENABLE 0x1
|
|
||||||
#define CONTROLLER_DISABLE 0x0
|
|
||||||
#define CRYPTO_GENERAL_ENABLE 0x2
|
|
||||||
|
|
||||||
/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
|
|
||||||
#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
|
|
||||||
#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
|
|
||||||
#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
|
|
||||||
#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
|
|
||||||
|
|
||||||
/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
|
|
||||||
#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
|
|
||||||
|
|
||||||
/* UECN - Host UIC Error Code Network Layer 40h */
|
|
||||||
#define UIC_NETWORK_LAYER_ERROR 0x80000000
|
|
||||||
#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
|
|
||||||
#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
|
|
||||||
#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
|
|
||||||
#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
|
|
||||||
|
|
||||||
/* UECT - Host UIC Error Code Transport Layer 44h */
|
|
||||||
#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
|
|
||||||
#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
|
|
||||||
#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
|
|
||||||
#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
|
|
||||||
#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
|
|
||||||
#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
|
|
||||||
#define UIC_TRANSPORT_BAD_TC 0x10
|
|
||||||
#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
|
|
||||||
#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
|
|
||||||
|
|
||||||
/* UECDME - Host UIC Error Code DME 48h */
|
|
||||||
#define UIC_DME_ERROR 0x80000000
|
|
||||||
#define UIC_DME_ERROR_CODE_MASK 0x1
|
|
||||||
|
|
||||||
/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
|
|
||||||
#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
|
|
||||||
#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
|
|
||||||
#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
|
|
||||||
#define INT_AGGR_STATUS_BIT 0x100000
|
|
||||||
#define INT_AGGR_PARAM_WRITE 0x1000000
|
|
||||||
#define INT_AGGR_ENABLE 0x80000000
|
|
||||||
|
|
||||||
/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
|
|
||||||
#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
|
|
||||||
|
|
||||||
/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
|
|
||||||
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
|
|
||||||
|
|
||||||
/* UICCMD - UIC Command */
|
|
||||||
#define COMMAND_OPCODE_MASK 0xFF
|
|
||||||
#define GEN_SELECTOR_INDEX_MASK 0xFFFF
|
|
||||||
|
|
||||||
#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
|
|
||||||
#define RESET_LEVEL 0xFF
|
|
||||||
|
|
||||||
#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
|
|
||||||
#define CONFIG_RESULT_CODE_MASK 0xFF
|
|
||||||
#define GENERIC_ERROR_CODE_MASK 0xFF
|
|
||||||
|
|
||||||
/* GenSelectorIndex calculation macros for M-PHY attributes */
|
|
||||||
#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
|
|
||||||
#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
|
|
||||||
|
|
||||||
#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
|
|
||||||
((sel) & 0xFFFF))
|
|
||||||
#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
|
|
||||||
#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
|
|
||||||
#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
|
|
||||||
|
|
||||||
/* Link Status*/
|
|
||||||
enum link_status {
|
|
||||||
UFSHCD_LINK_IS_DOWN = 1,
|
|
||||||
UFSHCD_LINK_IS_UP = 2,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UIC Commands */
|
|
||||||
enum uic_cmd_dme {
|
|
||||||
UIC_CMD_DME_GET = 0x01,
|
|
||||||
UIC_CMD_DME_SET = 0x02,
|
|
||||||
UIC_CMD_DME_PEER_GET = 0x03,
|
|
||||||
UIC_CMD_DME_PEER_SET = 0x04,
|
|
||||||
UIC_CMD_DME_POWERON = 0x10,
|
|
||||||
UIC_CMD_DME_POWEROFF = 0x11,
|
|
||||||
UIC_CMD_DME_ENABLE = 0x12,
|
|
||||||
UIC_CMD_DME_RESET = 0x14,
|
|
||||||
UIC_CMD_DME_END_PT_RST = 0x15,
|
|
||||||
UIC_CMD_DME_LINK_STARTUP = 0x16,
|
|
||||||
UIC_CMD_DME_HIBER_ENTER = 0x17,
|
|
||||||
UIC_CMD_DME_HIBER_EXIT = 0x18,
|
|
||||||
UIC_CMD_DME_TEST_MODE = 0x1A,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UIC Config result code / Generic error code */
|
|
||||||
enum {
|
|
||||||
UIC_CMD_RESULT_SUCCESS = 0x00,
|
|
||||||
UIC_CMD_RESULT_INVALID_ATTR = 0x01,
|
|
||||||
UIC_CMD_RESULT_FAILURE = 0x01,
|
|
||||||
UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
|
|
||||||
UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
|
|
||||||
UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
|
|
||||||
UIC_CMD_RESULT_BAD_INDEX = 0x05,
|
|
||||||
UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
|
|
||||||
UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
|
|
||||||
UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
|
|
||||||
UIC_CMD_RESULT_BUSY = 0x09,
|
|
||||||
UIC_CMD_RESULT_DME_FAILURE = 0x0A,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define MASK_UIC_COMMAND_RESULT 0xFF
|
|
||||||
|
|
||||||
#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
|
|
||||||
#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
|
|
||||||
|
|
||||||
/* Interrupt disable masks */
|
|
||||||
enum {
|
|
||||||
/* Interrupt disable mask for UFSHCI v1.0 */
|
|
||||||
INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
|
|
||||||
INTERRUPT_MASK_RW_VER_10 = 0x30000,
|
|
||||||
|
|
||||||
/* Interrupt disable mask for UFSHCI v1.1 */
|
|
||||||
INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
|
|
||||||
|
|
||||||
/* Interrupt disable mask for UFSHCI v2.1 */
|
|
||||||
INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* CCAP - Crypto Capability 100h */
|
|
||||||
union ufs_crypto_capabilities {
|
|
||||||
__le32 reg_val;
|
|
||||||
struct {
|
|
||||||
u8 num_crypto_cap;
|
|
||||||
u8 config_count;
|
|
||||||
u8 reserved;
|
|
||||||
u8 config_array_ptr;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_crypto_key_size {
|
|
||||||
UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
|
|
||||||
UFS_CRYPTO_KEY_SIZE_128 = 0x1,
|
|
||||||
UFS_CRYPTO_KEY_SIZE_192 = 0x2,
|
|
||||||
UFS_CRYPTO_KEY_SIZE_256 = 0x3,
|
|
||||||
UFS_CRYPTO_KEY_SIZE_512 = 0x4,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_crypto_alg {
|
|
||||||
UFS_CRYPTO_ALG_AES_XTS = 0x0,
|
|
||||||
UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
|
|
||||||
UFS_CRYPTO_ALG_AES_ECB = 0x2,
|
|
||||||
UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* x-CRYPTOCAP - Crypto Capability X */
|
|
||||||
union ufs_crypto_cap_entry {
|
|
||||||
__le32 reg_val;
|
|
||||||
struct {
|
|
||||||
u8 algorithm_id;
|
|
||||||
u8 sdus_mask; /* Supported data unit size mask */
|
|
||||||
u8 key_size;
|
|
||||||
u8 reserved;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
|
|
||||||
#define UFS_CRYPTO_KEY_MAX_SIZE 64
|
|
||||||
/* x-CRYPTOCFG - Crypto Configuration X */
|
|
||||||
union ufs_crypto_cfg_entry {
|
|
||||||
__le32 reg_val[32];
|
|
||||||
struct {
|
|
||||||
u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
|
|
||||||
u8 data_unit_size;
|
|
||||||
u8 crypto_cap_idx;
|
|
||||||
u8 reserved_1;
|
|
||||||
u8 config_enable;
|
|
||||||
u8 reserved_multi_host;
|
|
||||||
u8 reserved_2;
|
|
||||||
u8 vsb[2];
|
|
||||||
u8 reserved_3[56];
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Request Descriptor Definitions
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Transfer request command type */
|
|
||||||
enum {
|
|
||||||
UTP_CMD_TYPE_SCSI = 0x0,
|
|
||||||
UTP_CMD_TYPE_UFS = 0x1,
|
|
||||||
UTP_CMD_TYPE_DEV_MANAGE = 0x2,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* To accommodate UFS2.0 required Command type */
|
|
||||||
enum {
|
|
||||||
UTP_CMD_TYPE_UFS_STORAGE = 0x1,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum {
|
|
||||||
UTP_SCSI_COMMAND = 0x00000000,
|
|
||||||
UTP_NATIVE_UFS_COMMAND = 0x10000000,
|
|
||||||
UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
|
|
||||||
UTP_REQ_DESC_INT_CMD = 0x01000000,
|
|
||||||
UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* UTP Transfer Request Data Direction (DD) */
|
|
||||||
enum {
|
|
||||||
UTP_NO_DATA_TRANSFER = 0x00000000,
|
|
||||||
UTP_HOST_TO_DEVICE = 0x02000000,
|
|
||||||
UTP_DEVICE_TO_HOST = 0x04000000,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Overall command status values */
|
|
||||||
enum utp_ocs {
|
|
||||||
OCS_SUCCESS = 0x0,
|
|
||||||
OCS_INVALID_CMD_TABLE_ATTR = 0x1,
|
|
||||||
OCS_INVALID_PRDT_ATTR = 0x2,
|
|
||||||
OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
|
|
||||||
OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
|
|
||||||
OCS_PEER_COMM_FAILURE = 0x5,
|
|
||||||
OCS_ABORTED = 0x6,
|
|
||||||
OCS_FATAL_ERROR = 0x7,
|
|
||||||
OCS_DEVICE_FATAL_ERROR = 0x8,
|
|
||||||
OCS_INVALID_CRYPTO_CONFIG = 0x9,
|
|
||||||
OCS_GENERAL_CRYPTO_ERROR = 0xA,
|
|
||||||
OCS_INVALID_COMMAND_STATUS = 0x0F,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum {
|
|
||||||
MASK_OCS = 0x0F,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* The maximum length of the data byte count field in the PRDT is 256KB */
|
|
||||||
#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
|
|
||||||
/* The granularity of the data byte count field in the PRDT is 32-bit */
|
|
||||||
#define PRDT_DATA_BYTE_COUNT_PAD 4
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct ufshcd_sg_entry - UFSHCI PRD Entry
|
|
||||||
* @addr: Physical address; DW-0 and DW-1.
|
|
||||||
* @reserved: Reserved for future use DW-2
|
|
||||||
* @size: size of physical segment DW-3
|
|
||||||
*/
|
|
||||||
struct ufshcd_sg_entry {
|
|
||||||
__le64 addr;
|
|
||||||
__le32 reserved;
|
|
||||||
__le32 size;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
|
|
||||||
* @command_upiu: Command UPIU Frame address
|
|
||||||
* @response_upiu: Response UPIU Frame address
|
|
||||||
* @prd_table: Physical Region Descriptor
|
|
||||||
*/
|
|
||||||
struct utp_transfer_cmd_desc {
|
|
||||||
u8 command_upiu[ALIGNED_UPIU_SIZE];
|
|
||||||
u8 response_upiu[ALIGNED_UPIU_SIZE];
|
|
||||||
struct ufshcd_sg_entry prd_table[SG_ALL];
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
|
|
||||||
* @dword0: Descriptor Header DW0
|
|
||||||
* @dword1: Descriptor Header DW1
|
|
||||||
* @dword2: Descriptor Header DW2
|
|
||||||
* @dword3: Descriptor Header DW3
|
|
||||||
*/
|
|
||||||
struct request_desc_header {
|
|
||||||
__le32 dword_0;
|
|
||||||
__le32 dword_1;
|
|
||||||
__le32 dword_2;
|
|
||||||
__le32 dword_3;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
|
|
||||||
* @header: UTRD header DW-0 to DW-3
|
|
||||||
* @command_desc_base_addr_lo: UCD base address low DW-4
|
|
||||||
* @command_desc_base_addr_hi: UCD base address high DW-5
|
|
||||||
* @response_upiu_length: response UPIU length DW-6
|
|
||||||
* @response_upiu_offset: response UPIU offset DW-6
|
|
||||||
* @prd_table_length: Physical region descriptor length DW-7
|
|
||||||
* @prd_table_offset: Physical region descriptor offset DW-7
|
|
||||||
*/
|
|
||||||
struct utp_transfer_req_desc {
|
|
||||||
|
|
||||||
/* DW 0-3 */
|
|
||||||
struct request_desc_header header;
|
|
||||||
|
|
||||||
/* DW 4-5*/
|
|
||||||
__le32 command_desc_base_addr_lo;
|
|
||||||
__le32 command_desc_base_addr_hi;
|
|
||||||
|
|
||||||
/* DW 6 */
|
|
||||||
__le16 response_upiu_length;
|
|
||||||
__le16 response_upiu_offset;
|
|
||||||
|
|
||||||
/* DW 7 */
|
|
||||||
__le16 prd_table_length;
|
|
||||||
__le16 prd_table_offset;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* UTMRD structure.
|
|
||||||
*/
|
|
||||||
struct utp_task_req_desc {
|
|
||||||
/* DW 0-3 */
|
|
||||||
struct request_desc_header header;
|
|
||||||
|
|
||||||
/* DW 4-11 - Task request UPIU structure */
|
|
||||||
struct {
|
|
||||||
struct utp_upiu_header req_header;
|
|
||||||
__be32 input_param1;
|
|
||||||
__be32 input_param2;
|
|
||||||
__be32 input_param3;
|
|
||||||
__be32 __reserved1[2];
|
|
||||||
} upiu_req;
|
|
||||||
|
|
||||||
/* DW 12-19 - Task Management Response UPIU structure */
|
|
||||||
struct {
|
|
||||||
struct utp_upiu_header rsp_header;
|
|
||||||
__be32 output_param1;
|
|
||||||
__be32 output_param2;
|
|
||||||
__be32 __reserved2[3];
|
|
||||||
} upiu_rsp;
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* End of Header */
|
|
||||||
@@ -1,332 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
||||||
/*
|
|
||||||
* drivers/scsi/ufs/unipro.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _UNIPRO_H_
|
|
||||||
#define _UNIPRO_H_
|
|
||||||
|
|
||||||
/*
|
|
||||||
* M-TX Configuration Attributes
|
|
||||||
*/
|
|
||||||
#define TX_HIBERN8TIME_CAPABILITY 0x000F
|
|
||||||
#define TX_MODE 0x0021
|
|
||||||
#define TX_HSRATE_SERIES 0x0022
|
|
||||||
#define TX_HSGEAR 0x0023
|
|
||||||
#define TX_PWMGEAR 0x0024
|
|
||||||
#define TX_AMPLITUDE 0x0025
|
|
||||||
#define TX_HS_SLEWRATE 0x0026
|
|
||||||
#define TX_SYNC_SOURCE 0x0027
|
|
||||||
#define TX_HS_SYNC_LENGTH 0x0028
|
|
||||||
#define TX_HS_PREPARE_LENGTH 0x0029
|
|
||||||
#define TX_LS_PREPARE_LENGTH 0x002A
|
|
||||||
#define TX_HIBERN8_CONTROL 0x002B
|
|
||||||
#define TX_LCC_ENABLE 0x002C
|
|
||||||
#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D
|
|
||||||
#define TX_BYPASS_8B10B_ENABLE 0x002E
|
|
||||||
#define TX_DRIVER_POLARITY 0x002F
|
|
||||||
#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030
|
|
||||||
#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031
|
|
||||||
#define TX_LCC_SEQUENCER 0x0032
|
|
||||||
#define TX_MIN_ACTIVATETIME 0x0033
|
|
||||||
#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
|
|
||||||
#define TX_REFCLKFREQ 0x00EB
|
|
||||||
#define TX_CFGCLKFREQVAL 0x00EC
|
|
||||||
#define CFGEXTRATTR 0x00F0
|
|
||||||
#define DITHERCTRL2 0x00F1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* M-RX Configuration Attributes
|
|
||||||
*/
|
|
||||||
#define RX_MODE 0x00A1
|
|
||||||
#define RX_HSRATE_SERIES 0x00A2
|
|
||||||
#define RX_HSGEAR 0x00A3
|
|
||||||
#define RX_PWMGEAR 0x00A4
|
|
||||||
#define RX_LS_TERMINATED_ENABLE 0x00A5
|
|
||||||
#define RX_HS_UNTERMINATED_ENABLE 0x00A6
|
|
||||||
#define RX_ENTER_HIBERN8 0x00A7
|
|
||||||
#define RX_BYPASS_8B10B_ENABLE 0x00A8
|
|
||||||
#define RX_TERMINATION_FORCE_ENABLE 0x00A9
|
|
||||||
#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
|
|
||||||
#define RX_HIBERN8TIME_CAPABILITY 0x0092
|
|
||||||
#define RX_REFCLKFREQ 0x00EB
|
|
||||||
#define RX_CFGCLKFREQVAL 0x00EC
|
|
||||||
#define CFGWIDEINLN 0x00F0
|
|
||||||
#define CFGRXCDR8 0x00BA
|
|
||||||
#define ENARXDIRECTCFG4 0x00F2
|
|
||||||
#define CFGRXOVR8 0x00BD
|
|
||||||
#define RXDIRECTCTRL2 0x00C7
|
|
||||||
#define ENARXDIRECTCFG3 0x00F3
|
|
||||||
#define RXCALCTRL 0x00B4
|
|
||||||
#define ENARXDIRECTCFG2 0x00F4
|
|
||||||
#define CFGRXOVR4 0x00E9
|
|
||||||
#define RXSQCTRL 0x00B5
|
|
||||||
#define CFGRXOVR6 0x00BF
|
|
||||||
#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B
|
|
||||||
#define RX_HS_G1_PREP_LENGTH_CAP 0x008C
|
|
||||||
#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094
|
|
||||||
#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095
|
|
||||||
#define RX_HS_G2_PREP_LENGTH_CAP 0x0096
|
|
||||||
#define RX_HS_G3_PREP_LENGTH_CAP 0x0097
|
|
||||||
#define RX_ADV_GRANULARITY_CAP 0x0098
|
|
||||||
#define RX_MIN_ACTIVATETIME_CAP 0x008F
|
|
||||||
#define RX_HIBERN8TIME_CAP 0x0092
|
|
||||||
#define RX_ADV_HIBERN8TIME_CAP 0x0099
|
|
||||||
#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A
|
|
||||||
|
|
||||||
|
|
||||||
#define is_mphy_tx_attr(attr) (attr < RX_MODE)
|
|
||||||
#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
|
|
||||||
#define SYNC_LEN_FINE(x) ((x) & 0x3F)
|
|
||||||
#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F))
|
|
||||||
#define PREP_LEN(x) ((x) & 0xF)
|
|
||||||
|
|
||||||
#define RX_MIN_ACTIVATETIME_UNIT_US 100
|
|
||||||
#define HIBERN8TIME_UNIT_US 100
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Common Block Attributes
|
|
||||||
*/
|
|
||||||
#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B)
|
|
||||||
#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF)
|
|
||||||
#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD)
|
|
||||||
#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6)
|
|
||||||
#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA)
|
|
||||||
#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0)
|
|
||||||
#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1)
|
|
||||||
#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3)
|
|
||||||
#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
|
|
||||||
#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
|
|
||||||
|
|
||||||
#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PHY Adpater attributes
|
|
||||||
*/
|
|
||||||
#define PA_ACTIVETXDATALANES 0x1560
|
|
||||||
#define PA_ACTIVERXDATALANES 0x1580
|
|
||||||
#define PA_TXTRAILINGCLOCKS 0x1564
|
|
||||||
#define PA_PHY_TYPE 0x1500
|
|
||||||
#define PA_AVAILTXDATALANES 0x1520
|
|
||||||
#define PA_AVAILRXDATALANES 0x1540
|
|
||||||
#define PA_MINRXTRAILINGCLOCKS 0x1543
|
|
||||||
#define PA_TXPWRSTATUS 0x1567
|
|
||||||
#define PA_RXPWRSTATUS 0x1582
|
|
||||||
#define PA_TXFORCECLOCK 0x1562
|
|
||||||
#define PA_TXPWRMODE 0x1563
|
|
||||||
#define PA_LEGACYDPHYESCDL 0x1570
|
|
||||||
#define PA_MAXTXSPEEDFAST 0x1521
|
|
||||||
#define PA_MAXTXSPEEDSLOW 0x1522
|
|
||||||
#define PA_MAXRXSPEEDFAST 0x1541
|
|
||||||
#define PA_MAXRXSPEEDSLOW 0x1542
|
|
||||||
#define PA_TXLINKSTARTUPHS 0x1544
|
|
||||||
#define PA_LOCAL_TX_LCC_ENABLE 0x155E
|
|
||||||
#define PA_TXSPEEDFAST 0x1565
|
|
||||||
#define PA_TXSPEEDSLOW 0x1566
|
|
||||||
#define PA_REMOTEVERINFO 0x15A0
|
|
||||||
#define PA_TXGEAR 0x1568
|
|
||||||
#define PA_TXTERMINATION 0x1569
|
|
||||||
#define PA_HSSERIES 0x156A
|
|
||||||
#define PA_PWRMODE 0x1571
|
|
||||||
#define PA_RXGEAR 0x1583
|
|
||||||
#define PA_RXTERMINATION 0x1584
|
|
||||||
#define PA_MAXRXPWMGEAR 0x1586
|
|
||||||
#define PA_MAXRXHSGEAR 0x1587
|
|
||||||
#define PA_RXHSUNTERMCAP 0x15A5
|
|
||||||
#define PA_RXLSTERMCAP 0x15A6
|
|
||||||
#define PA_GRANULARITY 0x15AA
|
|
||||||
#define PA_PACPREQTIMEOUT 0x1590
|
|
||||||
#define PA_PACPREQEOBTIMEOUT 0x1591
|
|
||||||
#define PA_HIBERN8TIME 0x15A7
|
|
||||||
#define PA_LOCALVERINFO 0x15A9
|
|
||||||
#define PA_GRANULARITY 0x15AA
|
|
||||||
#define PA_TACTIVATE 0x15A8
|
|
||||||
#define PA_PACPFRAMECOUNT 0x15C0
|
|
||||||
#define PA_PACPERRORCOUNT 0x15C1
|
|
||||||
#define PA_PHYTESTCONTROL 0x15C2
|
|
||||||
#define PA_PWRMODEUSERDATA0 0x15B0
|
|
||||||
#define PA_PWRMODEUSERDATA1 0x15B1
|
|
||||||
#define PA_PWRMODEUSERDATA2 0x15B2
|
|
||||||
#define PA_PWRMODEUSERDATA3 0x15B3
|
|
||||||
#define PA_PWRMODEUSERDATA4 0x15B4
|
|
||||||
#define PA_PWRMODEUSERDATA5 0x15B5
|
|
||||||
#define PA_PWRMODEUSERDATA6 0x15B6
|
|
||||||
#define PA_PWRMODEUSERDATA7 0x15B7
|
|
||||||
#define PA_PWRMODEUSERDATA8 0x15B8
|
|
||||||
#define PA_PWRMODEUSERDATA9 0x15B9
|
|
||||||
#define PA_PWRMODEUSERDATA10 0x15BA
|
|
||||||
#define PA_PWRMODEUSERDATA11 0x15BB
|
|
||||||
#define PA_CONNECTEDTXDATALANES 0x1561
|
|
||||||
#define PA_CONNECTEDRXDATALANES 0x1581
|
|
||||||
#define PA_LOGICALLANEMAP 0x15A1
|
|
||||||
#define PA_SLEEPNOCONFIGTIME 0x15A2
|
|
||||||
#define PA_STALLNOCONFIGTIME 0x15A3
|
|
||||||
#define PA_SAVECONFIGTIME 0x15A4
|
|
||||||
#define PA_TXHSADAPTTYPE 0x15D4
|
|
||||||
|
|
||||||
/* Adpat type for PA_TXHSADAPTTYPE attribute */
|
|
||||||
#define PA_REFRESH_ADAPT 0x00
|
|
||||||
#define PA_INITIAL_ADAPT 0x01
|
|
||||||
#define PA_NO_ADAPT 0x03
|
|
||||||
|
|
||||||
#define PA_TACTIVATE_TIME_UNIT_US 10
|
|
||||||
#define PA_HIBERN8_TIME_UNIT_US 100
|
|
||||||
|
|
||||||
/*Other attributes*/
|
|
||||||
#define VS_MPHYCFGUPDT 0xD085
|
|
||||||
#define VS_DEBUGOMC 0xD09E
|
|
||||||
#define VS_POWERSTATE 0xD083
|
|
||||||
|
|
||||||
#define PA_GRANULARITY_MIN_VAL 1
|
|
||||||
#define PA_GRANULARITY_MAX_VAL 6
|
|
||||||
|
|
||||||
/* PHY Adapter Protocol Constants */
|
|
||||||
#define PA_MAXDATALANES 4
|
|
||||||
|
|
||||||
#define DL_FC0ProtectionTimeOutVal_Default 8191
|
|
||||||
#define DL_TC0ReplayTimeOutVal_Default 65535
|
|
||||||
#define DL_AFC0ReqTimeOutVal_Default 32767
|
|
||||||
#define DL_FC1ProtectionTimeOutVal_Default 8191
|
|
||||||
#define DL_TC1ReplayTimeOutVal_Default 65535
|
|
||||||
#define DL_AFC1ReqTimeOutVal_Default 32767
|
|
||||||
|
|
||||||
#define DME_LocalFC0ProtectionTimeOutVal 0xD041
|
|
||||||
#define DME_LocalTC0ReplayTimeOutVal 0xD042
|
|
||||||
#define DME_LocalAFC0ReqTimeOutVal 0xD043
|
|
||||||
|
|
||||||
/* PA power modes */
|
|
||||||
enum {
|
|
||||||
FAST_MODE = 1,
|
|
||||||
SLOW_MODE = 2,
|
|
||||||
FASTAUTO_MODE = 4,
|
|
||||||
SLOWAUTO_MODE = 5,
|
|
||||||
UNCHANGED = 7,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define PWRMODE_MASK 0xF
|
|
||||||
#define PWRMODE_RX_OFFSET 4
|
|
||||||
|
|
||||||
/* PA TX/RX Frequency Series */
|
|
||||||
enum {
|
|
||||||
PA_HS_MODE_A = 1,
|
|
||||||
PA_HS_MODE_B = 2,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_pwm_gear_tag {
|
|
||||||
UFS_PWM_DONT_CHANGE, /* Don't change Gear */
|
|
||||||
UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
|
|
||||||
UFS_PWM_G2, /* PWM Gear 2 */
|
|
||||||
UFS_PWM_G3, /* PWM Gear 3 */
|
|
||||||
UFS_PWM_G4, /* PWM Gear 4 */
|
|
||||||
UFS_PWM_G5, /* PWM Gear 5 */
|
|
||||||
UFS_PWM_G6, /* PWM Gear 6 */
|
|
||||||
UFS_PWM_G7, /* PWM Gear 7 */
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_hs_gear_tag {
|
|
||||||
UFS_HS_DONT_CHANGE, /* Don't change Gear */
|
|
||||||
UFS_HS_G1, /* HS Gear 1 (default for reset) */
|
|
||||||
UFS_HS_G2, /* HS Gear 2 */
|
|
||||||
UFS_HS_G3, /* HS Gear 3 */
|
|
||||||
UFS_HS_G4, /* HS Gear 4 */
|
|
||||||
};
|
|
||||||
|
|
||||||
enum ufs_unipro_ver {
|
|
||||||
UFS_UNIPRO_VER_RESERVED = 0,
|
|
||||||
UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
|
|
||||||
UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
|
|
||||||
UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
|
|
||||||
UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */
|
|
||||||
UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */
|
|
||||||
UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */
|
|
||||||
/* UniPro version field mask in PA_LOCALVERINFO */
|
|
||||||
UFS_UNIPRO_VER_MASK = 0xF,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Data Link Layer Attributes
|
|
||||||
*/
|
|
||||||
#define DL_TC0TXFCTHRESHOLD 0x2040
|
|
||||||
#define DL_FC0PROTTIMEOUTVAL 0x2041
|
|
||||||
#define DL_TC0REPLAYTIMEOUTVAL 0x2042
|
|
||||||
#define DL_AFC0REQTIMEOUTVAL 0x2043
|
|
||||||
#define DL_AFC0CREDITTHRESHOLD 0x2044
|
|
||||||
#define DL_TC0OUTACKTHRESHOLD 0x2045
|
|
||||||
#define DL_TC1TXFCTHRESHOLD 0x2060
|
|
||||||
#define DL_FC1PROTTIMEOUTVAL 0x2061
|
|
||||||
#define DL_TC1REPLAYTIMEOUTVAL 0x2062
|
|
||||||
#define DL_AFC1REQTIMEOUTVAL 0x2063
|
|
||||||
#define DL_AFC1CREDITTHRESHOLD 0x2064
|
|
||||||
#define DL_TC1OUTACKTHRESHOLD 0x2065
|
|
||||||
#define DL_TXPREEMPTIONCAP 0x2000
|
|
||||||
#define DL_TC0TXMAXSDUSIZE 0x2001
|
|
||||||
#define DL_TC0RXINITCREDITVAL 0x2002
|
|
||||||
#define DL_TC0TXBUFFERSIZE 0x2005
|
|
||||||
#define DL_PEERTC0PRESENT 0x2046
|
|
||||||
#define DL_PEERTC0RXINITCREVAL 0x2047
|
|
||||||
#define DL_TC1TXMAXSDUSIZE 0x2003
|
|
||||||
#define DL_TC1RXINITCREDITVAL 0x2004
|
|
||||||
#define DL_TC1TXBUFFERSIZE 0x2006
|
|
||||||
#define DL_PEERTC1PRESENT 0x2066
|
|
||||||
#define DL_PEERTC1RXINITCREVAL 0x2067
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Network Layer Attributes
|
|
||||||
*/
|
|
||||||
#define N_DEVICEID 0x3000
|
|
||||||
#define N_DEVICEID_VALID 0x3001
|
|
||||||
#define N_TC0TXMAXSDUSIZE 0x3020
|
|
||||||
#define N_TC1TXMAXSDUSIZE 0x3021
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Transport Layer Attributes
|
|
||||||
*/
|
|
||||||
#define T_NUMCPORTS 0x4000
|
|
||||||
#define T_NUMTESTFEATURES 0x4001
|
|
||||||
#define T_CONNECTIONSTATE 0x4020
|
|
||||||
#define T_PEERDEVICEID 0x4021
|
|
||||||
#define T_PEERCPORTID 0x4022
|
|
||||||
#define T_TRAFFICCLASS 0x4023
|
|
||||||
#define T_PROTOCOLID 0x4024
|
|
||||||
#define T_CPORTFLAGS 0x4025
|
|
||||||
#define T_TXTOKENVALUE 0x4026
|
|
||||||
#define T_RXTOKENVALUE 0x4027
|
|
||||||
#define T_LOCALBUFFERSPACE 0x4028
|
|
||||||
#define T_PEERBUFFERSPACE 0x4029
|
|
||||||
#define T_CREDITSTOSEND 0x402A
|
|
||||||
#define T_CPORTMODE 0x402B
|
|
||||||
#define T_TC0TXMAXSDUSIZE 0x4060
|
|
||||||
#define T_TC1TXMAXSDUSIZE 0x4061
|
|
||||||
|
|
||||||
#ifdef FALSE
|
|
||||||
#undef FALSE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef TRUE
|
|
||||||
#undef TRUE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Boolean attribute values */
|
|
||||||
enum {
|
|
||||||
FALSE = 0,
|
|
||||||
TRUE,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* CPort setting */
|
|
||||||
#define E2EFC_ON (1 << 0)
|
|
||||||
#define E2EFC_OFF (0 << 0)
|
|
||||||
#define CSD_N_ON (0 << 1)
|
|
||||||
#define CSD_N_OFF (1 << 1)
|
|
||||||
#define CSV_N_ON (0 << 2)
|
|
||||||
#define CSV_N_OFF (1 << 2)
|
|
||||||
#define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF)
|
|
||||||
|
|
||||||
/* CPort connection state */
|
|
||||||
enum {
|
|
||||||
CPORT_IDLE = 0,
|
|
||||||
CPORT_CONNECTED,
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* _UNIPRO_H_ */
|
|
||||||
@@ -1,17 +1,11 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
/* Copyright (c) 2015-2023, The Linux Foundation. All rights reserved.
|
/* Copyright (c) 2015-2023, The Linux Foundation. All rights reserved. */
|
||||||
*/
|
/* SPDX-FileCopyrightText: Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
|
||||||
|
|
||||||
#ifndef UFSHCD_PLTFRM_H_
|
#ifndef UFSHCD_PLTFRM_H_
|
||||||
#define UFSHCD_PLTFRM_H_
|
#define UFSHCD_PLTFRM_H_
|
||||||
|
|
||||||
#include <nvidia/conftest.h>
|
|
||||||
|
|
||||||
#if defined(NV_UFS_UFSHCD_H_PRESENT)
|
|
||||||
#include <ufs/ufshcd.h>
|
#include <ufs/ufshcd.h>
|
||||||
#else
|
|
||||||
#include "ufshcd.h"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define UFS_PWM_MODE 1
|
#define UFS_PWM_MODE 1
|
||||||
#define UFS_HS_MODE 2
|
#define UFS_HS_MODE 2
|
||||||
|
|||||||
@@ -1,16 +1,10 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
// SPDX-FileCopyrightText: Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||||
|
|
||||||
#include <nvidia/conftest.h>
|
|
||||||
|
|
||||||
#include <linux/version.h>
|
#include <linux/version.h>
|
||||||
|
|
||||||
#if defined(NV_UFS_UFSHCD_H_PRESENT)
|
|
||||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 7, 0)
|
#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 7, 0)
|
||||||
#include <drivers-private/scsi/ufs/k61/ufshcd-priv.h>
|
#include <drivers-private/scsi/ufs/k61/ufshcd-priv.h>
|
||||||
#else
|
#else
|
||||||
#include <drivers-private/scsi/ufs/k67/ufshcd-priv.h>
|
#include <drivers-private/scsi/ufs/k67/ufshcd-priv.h>
|
||||||
#endif
|
#endif
|
||||||
#else /* NV_UFS_UFSHCD_H_PRESENT */
|
|
||||||
#error "This header should not be included"
|
|
||||||
#endif
|
|
||||||
|
|||||||
@@ -1,16 +0,0 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
||||||
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
|
||||||
|
|
||||||
#include <nvidia/conftest.h>
|
|
||||||
|
|
||||||
#include <linux/version.h>
|
|
||||||
|
|
||||||
#if defined(NV_UFS_UFSHCD_H_PRESENT)
|
|
||||||
#error "Use headers from core kernel"
|
|
||||||
#else /* NV_UFS_UFSHCD_H_PRESENT */
|
|
||||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)
|
|
||||||
#include <drivers-private/scsi/ufs/k515/ufshcd.h>
|
|
||||||
#else
|
|
||||||
#include <drivers-private/scsi/ufs/k516/ufshcd.h>
|
|
||||||
#endif
|
|
||||||
#endif /* NV_UFS_UFSHCD_H_PRESENT */
|
|
||||||
@@ -1,16 +0,0 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
||||||
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
|
||||||
|
|
||||||
#include <nvidia/conftest.h>
|
|
||||||
|
|
||||||
#include <linux/version.h>
|
|
||||||
|
|
||||||
#if defined(NV_UFS_UFSHCD_H_PRESENT)
|
|
||||||
#error "Include headers from core kernel"
|
|
||||||
#else
|
|
||||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)
|
|
||||||
#include <drivers-private/scsi/ufs/k515/ufshci.h>
|
|
||||||
#else
|
|
||||||
#include <drivers-private/scsi/ufs/k516/ufshci.h>
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
@@ -1,16 +0,0 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
||||||
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
|
||||||
|
|
||||||
#include <nvidia/conftest.h>
|
|
||||||
|
|
||||||
#include <linux/version.h>
|
|
||||||
|
|
||||||
#if defined(NV_UFS_UFSHCD_H_PRESENT)
|
|
||||||
#error "Use headers from core kernel"
|
|
||||||
#else
|
|
||||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)
|
|
||||||
#include <drivers-private/scsi/ufs/k515/unipro.h>
|
|
||||||
#else
|
|
||||||
#include <drivers-private/scsi/ufs/k516/unipro.h>
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
@@ -281,8 +281,7 @@ NV_HEADER_PRESENCE_TESTS = \
|
|||||||
linux/iosys-map.h \
|
linux/iosys-map.h \
|
||||||
linux/tegra_prod.h \
|
linux/tegra_prod.h \
|
||||||
net/gso.h \
|
net/gso.h \
|
||||||
net/page_pool.h \
|
net/page_pool.h
|
||||||
ufs/ufshcd.h
|
|
||||||
|
|
||||||
# Filename to store the define for the header in $(1); this is only consumed by
|
# Filename to store the define for the header in $(1); this is only consumed by
|
||||||
# the rule below that concatenates all of these together.
|
# the rule below that concatenates all of these together.
|
||||||
|
|||||||
@@ -8837,11 +8837,7 @@ compile_test() {
|
|||||||
# function making the 3rd argument of type const.
|
# function making the 3rd argument of type const.
|
||||||
#
|
#
|
||||||
CODE="
|
CODE="
|
||||||
#if defined(NV_UFS_UFSHCD_H_PRESENT)
|
|
||||||
#include <ufs/ufshcd.h>
|
#include <ufs/ufshcd.h>
|
||||||
#else
|
|
||||||
#include \"../drivers/scsi/ufs/ufshcd.h\"
|
|
||||||
#endif
|
|
||||||
void conftest(struct ufs_hba_variant_ops *ops) {
|
void conftest(struct ufs_hba_variant_ops *ops) {
|
||||||
int (*fn)(struct ufs_hba *hba,
|
int (*fn)(struct ufs_hba *hba,
|
||||||
enum ufs_notify_change_status status,
|
enum ufs_notify_change_status status,
|
||||||
@@ -8864,11 +8860,7 @@ compile_test() {
|
|||||||
# 'struct ufs_hba_variant_ops'.
|
# 'struct ufs_hba_variant_ops'.
|
||||||
#
|
#
|
||||||
CODE="
|
CODE="
|
||||||
#if defined(NV_UFS_UFSHCD_H_PRESENT)
|
|
||||||
#include <ufs/ufshcd.h>
|
#include <ufs/ufshcd.h>
|
||||||
#else
|
|
||||||
#include \"../drivers/scsi/ufs/ufshcd.h\"
|
|
||||||
#endif
|
|
||||||
void conftest_ufs_hba_variant_ops_suspend_has_status_arg(
|
void conftest_ufs_hba_variant_ops_suspend_has_status_arg(
|
||||||
struct ufs_hba_variant_ops *ops) {
|
struct ufs_hba_variant_ops *ops) {
|
||||||
int (*fn)(struct ufs_hba *, enum ufs_pm_op,
|
int (*fn)(struct ufs_hba *, enum ufs_pm_op,
|
||||||
|
|||||||
Reference in New Issue
Block a user