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dts: pwm: Add Tegra234 PWM controller

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Tegra234 has eight single-channel PWM controllers, one of them in the
AON block.

Enable required PMW controllers (i.e. User pwm, PWM-FAN etc)
of Orin dev-kit.

Bug 3771588

Change-Id: I7a8e741d62fb190487df5586ce397c7a965dcd07
Signed-off-by: Sandipan Patra <spatra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2795495
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sandipan Patra
2022-10-20 08:24:34 +00:00
committed by mobile promotions
parent 1cb49e59a3
commit bbde9d8b23
1 changed files with 98 additions and 0 deletions
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98
arch/arm64/boot/dts/nvidia/tegra234-soc-overlay.dtsi
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@@ -615,4 +615,102 @@
};
};
};
fragment-t234@6 {
target-path = "/bus@0/pwm@3280000";
__overlay__ {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
status = "okay";
};
};
fragment-t234@7 {
target-path = "/bus@0";
__overlay__ {
pwm2: pwm@3290000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x3290000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM2>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM2>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm3: pwm@32a0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32a0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM3>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM3>;
reset-names = "pwm";
status = "okay";
#pwm-cells = <2>;
};
pwm4: pwm@c340000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0xc340000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM4>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM4>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm5: pwm@32c0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32c0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM5>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM5>;
reset-names = "pwm";
status = "okay";
#pwm-cells = <2>;
};
pwm6: pwm@32d0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32d0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM6>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM6>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm7: pwm@32e0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32e0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM7>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM7>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm8: pwm@32f0000 {
compatible = "nvidia,tegra234-pwm",
"nvidia,tegra194-pwm";
reg = <0x32f0000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM8>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM8>;
reset-names = "pwm";
status = "okay";
#pwm-cells = <2>;
};
};
};
};