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media: tegra: cdi-mgr: support interrupt timeouts

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Add support for configurable interrupt timers and event notification
queues to SIPL Device Block to mirror the CDAC (QNX) pulse channel
interface.

The CDI_MGR_IOCTL_INTR_CONFIG IOCTL is added to set the timeout
duration at initialization, and existing GPIO interrupt code is
refactored.

Also removes the GPIO index limitation to the range of [0,31] by
returning the complete indices one at a time instead of a bit flag.

Jira CAMERASW-11100
Jira CAMERASW-11385
Jira CAMERASW-9366

Bug 3902416
Bug 3792904

Signed-off-by: Vincent Chung <vincentc@nvidia.com>
Change-Id: I62b6c0bd8be18922ab1fe5d40485a69274f2a18e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2893327
Reviewed-by: Semi Malinen <smalinen@nvidia.com>
Reviewed-by: Shiva Dubey <sdubey@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Vincent Chung
2023-03-11 18:20:00 -08:00
committed by mobile promotions
parent 5dcd80a533
commit be01df015d
3 changed files with 465 additions and 116 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
include/uapi/media/cdi-mgr.h
View File

@@ -7,22 +7,23 @@
#include <linux/ioctl.h>
#include <linux/types.h>
#define CDI_MGR_IOCTL_PWR_DN _IOW('o', 1, __s16)
#define CDI_MGR_IOCTL_PWR_UP _IOR('o', 2, __s16)
#define CDI_MGR_IOCTL_SET_PID _IOW('o', 3, struct cdi_mgr_sinfo)
#define CDI_MGR_IOCTL_SIGNAL _IOW('o', 4, int)
#define CDI_MGR_IOCTL_DEV_ADD _IOW('o', 5, struct cdi_mgr_new_dev)
#define CDI_MGR_IOCTL_DEV_DEL _IOW('o', 6, int)
#define CDI_MGR_IOCTL_PWR_INFO _IOW('o', 7, struct cdi_mgr_pwr_info)
#define CDI_MGR_IOCTL_PWM_ENABLE _IOW('o', 8, int)
#define CDI_MGR_IOCTL_PWM_CONFIG _IOW('o', 9, struct cdi_mgr_pwm_info)
#define CDI_MGR_IOCTL_WAIT_ERR _IOWR('o', 10, __u32)
#define CDI_MGR_IOCTL_ABORT_WAIT_ERR _IO('o', 11)
#define CDI_MGR_IOCTL_GET_EXT_PWR_CTRL _IOR('o', 12, __u8)
#define CDI_MGR_IOCTL_ENABLE_ERROR_REPORT _IO('o', 13)
#define CDI_MGR_IOCTL_GET_PWR_INFO _IOW('o', 14, struct cdi_mgr_pwr_ctrl_info)
#define CDI_MGR_IOCTL_ENABLE_DES_POWER _IO('o', 15)
#define CDI_MGR_IOCTL_DISABLE_DES_POWER _IO('o', 16)
#define CDI_MGR_IOCTL_PWR_DN _IOW('o', 1, __s16)
#define CDI_MGR_IOCTL_PWR_UP _IOR('o', 2, __s16)
#define CDI_MGR_IOCTL_SET_PID _IOW('o', 3, struct cdi_mgr_sinfo)
#define CDI_MGR_IOCTL_SIGNAL _IOW('o', 4, int)
#define CDI_MGR_IOCTL_DEV_ADD _IOW('o', 5, struct cdi_mgr_new_dev)
#define CDI_MGR_IOCTL_DEV_DEL _IOW('o', 6, int)
#define CDI_MGR_IOCTL_PWR_INFO _IOW('o', 7, struct cdi_mgr_pwr_info)
#define CDI_MGR_IOCTL_PWM_ENABLE _IOW('o', 8, int)
#define CDI_MGR_IOCTL_PWM_CONFIG _IOW('o', 9, struct cdi_mgr_pwm_info)
#define CDI_MGR_IOCTL_INTR_CONFIG _IOW('o', 10, struct cdi_mgr_gpio_info)
#define CDI_MGR_IOCTL_INTR_ENABLE _IO('o', 11)
#define CDI_MGR_IOCTL_INTR_WAIT _IOR('o', 12, __u32)
#define CDI_MGR_IOCTL_INTR_WAIT_ABORT _IO('o', 13)
#define CDI_MGR_IOCTL_GET_EXT_PWR_CTRL _IOR('o', 14, __u8)
#define CDI_MGR_IOCTL_GET_PWR_INFO _IOW('o', 15, struct cdi_mgr_pwr_ctrl_info)
#define CDI_MGR_IOCTL_ENABLE_DES_POWER _IO('o', 16)
#define CDI_MGR_IOCTL_DISABLE_DES_POWER _IO('o', 17)
#define CDI_MGR_POWER_ALL 5
#define MAX_CDI_NAME_LENGTH 32
@@ -57,14 +58,26 @@ struct cdi_mgr_pwr_ctrl_info {
__s8 des_pwr_i2c_addr;
};
struct cdi_mgr_gpio_info {
__u32 idx;
__u32 timeout_ms;
};
struct cdi_mgr_gpio_intr {
__u32 idx;
__u32 code;
};
struct cdi_mgr_pwm_info {
__u64 duty_ns;
__u64 period_ns;
};
enum {
CDI_MGR_PWM_DISABLE = 0,
CDI_MGR_PWM_ENABLE,
CDI_MGR_GPIO_INTR_UNBLOCK = 0,
CDI_MGR_GPIO_INTR,
CDI_MGR_GPIO_INTR_TIMEOUT,
};
enum {
@@ -72,4 +85,9 @@ enum {
CDI_MGR_SIGNAL_SUSPEND,
};
enum {
CDI_MGR_PWM_DISABLE = 0,
CDI_MGR_PWM_ENABLE,
};
#endif /* __UAPI_TEGRA_CDI_MGR_H__ */