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ASoC: tegra-alt: Unify the tegra-alt drivers

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Unify the tegra alt drivers to support all chips.

Bug 200257345

Change-Id: Ie6bff2e421330b0fd9d1deb14f2afd1131d01a44
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Reviewed-on: http://git-master/r/1327760
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
This commit is contained in:
Mohan Kumar
2017-03-24 23:02:22 +05:30
committed by Sameer Pujar
parent 30d77a84d6
commit c85e969ca0
3 changed files with 6 additions and 22 deletions
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5
sound/soc/tegra-alt/tegra210_dmic_alt.c
View File

@@ -520,11 +520,8 @@ static int tegra210_dmic_platform_probe(struct platform_device *pdev)
ret = PTR_ERR(dmic->clk_dmic); ret = PTR_ERR(dmic->clk_dmic);
goto err; goto err;
} }
#if defined(CONFIG_ARCH_TEGRA_210_SOC)
dmic->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
#else
dmic->clk_pll_a_out0 = devm_clk_get(&pdev->dev, "pll_a_out0"); dmic->clk_pll_a_out0 = devm_clk_get(&pdev->dev, "pll_a_out0");
#endif
if (IS_ERR_OR_NULL(dmic->clk_pll_a_out0)) { if (IS_ERR_OR_NULL(dmic->clk_pll_a_out0)) {
dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n"); dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n");
ret = -ENOENT; ret = -ENOENT;

12
sound/soc/tegra-alt/tegra210_i2s_alt.c
View File

@@ -93,7 +93,7 @@ static int tegra210_i2s_set_clock_rate(struct device *dev, int clock_rate)
dev_err(dev, "Can't set I2S sync clock rate\n"); dev_err(dev, "Can't set I2S sync clock rate\n");
return ret; return ret;
} }
#if !defined(CONFIG_ARCH_TEGRA_210_SOC)
ret = clk_set_parent(i2s->clk_audio_sync, ret = clk_set_parent(i2s->clk_audio_sync,
i2s->clk_i2s_sync); i2s->clk_i2s_sync);
if (ret) { if (ret) {
@@ -101,7 +101,7 @@ static int tegra210_i2s_set_clock_rate(struct device *dev, int clock_rate)
"Can't set parent of i2s audio sync clock\n"); "Can't set parent of i2s audio sync clock\n");
return ret; return ret;
} }
#endif
ret = clk_set_parent(i2s->clk_i2s, i2s->clk_i2s_source); ret = clk_set_parent(i2s->clk_i2s, i2s->clk_i2s_source);
if (ret) { if (ret) {
dev_err(dev, "Can't set parent of I2S clock\n"); dev_err(dev, "Can't set parent of I2S clock\n");
@@ -1054,11 +1054,7 @@ static int tegra210_i2s_platform_probe(struct platform_device *pdev)
goto err_i2s_sync_clk_put; goto err_i2s_sync_clk_put;
} }
#if defined(CONFIG_ARCH_TEGRA_210_SOC)
i2s->clk_i2s_source = clk_get_sys(NULL, "pll_a_out0");
#else
i2s->clk_i2s_source = devm_clk_get(&pdev->dev, "pll_a_out0"); i2s->clk_i2s_source = devm_clk_get(&pdev->dev, "pll_a_out0");
#endif
if (IS_ERR(i2s->clk_i2s_source)) { if (IS_ERR(i2s->clk_i2s_source)) {
dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n"); dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n");
ret = PTR_ERR(i2s->clk_i2s_source); ret = PTR_ERR(i2s->clk_i2s_source);
@@ -1209,11 +1205,7 @@ err_pm_disable:
pm_runtime_disable(&pdev->dev); pm_runtime_disable(&pdev->dev);
err_pll_a_out0_clk_put: err_pll_a_out0_clk_put:
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
#if defined(CONFIG_ARCH_TEGRA_210_SOC)
clk_put(i2s->clk_i2s_source);
#else
devm_clk_put(&pdev->dev, i2s->clk_i2s_source); devm_clk_put(&pdev->dev, i2s->clk_i2s_source);
#endif
err_audio_sync_clk_put: err_audio_sync_clk_put:
devm_clk_put(&pdev->dev, i2s->clk_audio_sync); devm_clk_put(&pdev->dev, i2s->clk_audio_sync);
err_i2s_sync_clk_put: err_i2s_sync_clk_put:

11
sound/soc/tegra-alt/tegra210_spdif_alt.c
View File

@@ -171,14 +171,13 @@ static int tegra210_spdif_set_dai_sysclk(struct snd_soc_dai *dai,
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) { if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
if (dir == SND_SOC_CLOCK_OUT) { if (dir == SND_SOC_CLOCK_OUT) {
#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
ret = clk_set_parent(spdif->clk_spdif_out, ret = clk_set_parent(spdif->clk_spdif_out,
spdif->clk_pll_a_out0); spdif->clk_pll_a_out0);
if (ret) { if (ret) {
dev_err(dev, "Can't set parent of SPDIF OUT clock\n"); dev_err(dev, "Can't set parent of SPDIF OUT clock\n");
return ret; return ret;
} }
#endif
ret = clk_set_rate( ret = clk_set_rate(
spdif->clk_spdif_out, spdif_out_clock_rate); spdif->clk_spdif_out, spdif_out_clock_rate);
if (ret) { if (ret) {
@@ -187,14 +186,13 @@ static int tegra210_spdif_set_dai_sysclk(struct snd_soc_dai *dai,
return ret; return ret;
} }
} else { } else {
#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
ret = clk_set_parent(spdif->clk_spdif_in, ret = clk_set_parent(spdif->clk_spdif_in,
spdif->clk_pll_p_out0); spdif->clk_pll_p_out0);
if (ret) { if (ret) {
dev_err(dev, "Can't set parent of SPDIF IN clock\n"); dev_err(dev, "Can't set parent of SPDIF IN clock\n");
return ret; return ret;
} }
#endif
ret = clk_set_rate( ret = clk_set_rate(
spdif->clk_spdif_in, spdif_in_clock_rate); spdif->clk_spdif_in, spdif_in_clock_rate);
if (ret) { if (ret) {
@@ -474,7 +472,6 @@ static int tegra210_spdif_platform_probe(struct platform_device *pdev)
spdif->soc_data = soc_data; spdif->soc_data = soc_data;
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) { if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
spdif->clk_pll_a_out0 = devm_clk_get(&pdev->dev, "pll_a_out0"); spdif->clk_pll_a_out0 = devm_clk_get(&pdev->dev, "pll_a_out0");
if (IS_ERR(spdif->clk_pll_a_out0)) { if (IS_ERR(spdif->clk_pll_a_out0)) {
dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n"); dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n");
@@ -488,7 +485,7 @@ static int tegra210_spdif_platform_probe(struct platform_device *pdev)
ret = PTR_ERR(spdif->clk_pll_p_out0); ret = PTR_ERR(spdif->clk_pll_p_out0);
goto err_spdif_plla_clk_put; goto err_spdif_plla_clk_put;
} }
#endif
spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "spdif_out"); spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "spdif_out");
if (IS_ERR(spdif->clk_spdif_out)) { if (IS_ERR(spdif->clk_spdif_out)) {
dev_err(&pdev->dev, "Can't retrieve spdif clock\n"); dev_err(&pdev->dev, "Can't retrieve spdif clock\n");
@@ -615,13 +612,11 @@ err_spdif_out_clk_put:
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
devm_clk_put(&pdev->dev, spdif->clk_spdif_out); devm_clk_put(&pdev->dev, spdif->clk_spdif_out);
err_spdif_pllp_clk_put: err_spdif_pllp_clk_put:
#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
devm_clk_put(&pdev->dev, spdif->clk_pll_p_out0); devm_clk_put(&pdev->dev, spdif->clk_pll_p_out0);
err_spdif_plla_clk_put: err_spdif_plla_clk_put:
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
devm_clk_put(&pdev->dev, spdif->clk_pll_a_out0); devm_clk_put(&pdev->dev, spdif->clk_pll_a_out0);
#endif
err: err:
return ret; return ret;
} }