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drivers: pva: Update DMA desc patching

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When BL format is used, address-bit 39 needs to be set
only for T23x and older generations to indicate XBAR_RAW
swizzling is required.

Bug 4190882

Change-Id: I51805c9636bae8d3dec83b02e0665a4eb9657406
Signed-off-by: Amruta Bhamidipati <abhamidipati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2935382
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2999151
Reviewed-by: Krish Agarwal <krisha@nvidia.com>
Reviewed-by: Michael Chen (SW-TEGRA) <michaelch@nvidia.com>
Reviewed-by: Omar Nemri <onemri@nvidia.com>
Tested-by: Omar Nemri <onemri@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Amruta Bhamidipati
2023-07-12 20:29:53 +00:00
committed by mobile promotions
parent 827c90d801
commit ce5e1eadbb
1 changed files with 14 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/video/tegra/host/pva/pva_dma.c
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@@ -272,6 +272,7 @@ patch_dma_desc_address(struct pva_submit_task *task,
int32_t err = 0; int32_t err = 0;
uint64_t addr_base = 0; uint64_t addr_base = 0;
struct pva_dma_task_buffer_info_s *buff_info = &task->task_buff_info[desc_id]; struct pva_dma_task_buffer_info_s *buff_info = &task->task_buff_info[desc_id];
int hwgen = task->pva->version;
nvpva_dbg_fn(task->pva, ""); nvpva_dbg_fn(task->pva, "");
@@ -410,9 +411,12 @@ patch_dma_desc_address(struct pva_submit_task *task,
task->src_surf_base_addr = addr_base; task->src_surf_base_addr = addr_base;
buff_info->src_buffer_size = mem->size; buff_info->src_buffer_size = mem->size;
/** If BL format selected, set addr bit 39 to indicate */ /* If BL format selected, set addr bit 39 to indicate
/* XBAR_RAW swizzling is required */ * XBAR_RAW swizzling is required for PVA_HW_GEN2 and
addr_base |= (u64)umd_dma_desc->srcFormat << 39U; * older generations.
*/
if (hwgen <= PVA_HW_GEN2)
addr_base |= (u64)umd_dma_desc->srcFormat << 39U;
break; break;
} }
@@ -594,9 +598,13 @@ patch_dma_desc_address(struct pva_submit_task *task,
task->dst_surf_base_addr = addr_base; task->dst_surf_base_addr = addr_base;
buff_info->dst_buffer_size = mem->size; buff_info->dst_buffer_size = mem->size;
/* If BL format selected, set addr bit 39 to indicate */ /* If BL format selected, set addr bit 39 to indicate
/* XBAR_RAW swizzling is required */ * XBAR_RAW swizzling is required for PVA_HW_GEN2
addr_base |= (u64)umd_dma_desc->dstFormat << 39U; * and older generations.
*/
if (hwgen <= PVA_HW_GEN2)
addr_base |= (u64)umd_dma_desc->dstFormat << 39U;
break; break;
} }
case DMA_DESC_DST_XFER_R5TCM: case DMA_DESC_DST_XFER_R5TCM: