nvethernet: allow PHY read/write if MAC clks enabled

Issue: During system suspend, PHY framework is trying to
access the PHY registers even though the ethernet interface
is not up which inturn causing the bus errors since MAC clocks
not enabled.

Fix: Add MAC clocks enable check before accessing the PHY
registers through MDIO bus.

Bug 200548320

Change-Id: Ic85ae82bbc7e7f33203cc94f8407bdfd23f75502
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2187285
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/net/ethernet/nvidia/nvethernet/ether_linux.h

@@ -298,6 +298,8 @@ struct ether_priv_data {
 	unsigned int max_platform_mtu;
 	/** Spin lock for PTP registers */
 	raw_spinlock_t ptp_lock;
+	/** Clocks enable check */
+	bool clks_enable;
 };
 
 /**