ASoc: tegra-alt: utils: fix kernel panic

Initialise snd_soc_dapm_update struct with NULL
to avoid kernel panic

Commit e411b0b5eb9b ("ASoC: dapm: Support second
register for DAPM control updates") introduced a
2nd register set into the snd_soc_dapm_update struct
and if the 'has_second_set' is not initialised
then it tries to access bogus register.

bug 200406253

Change-Id: Ic18ba2bb990c1c13f595305a05e4fc60a4b0baee
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1697229
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Dara Ramesh
2018-04-18 10:29:38 +05:30
committed by Sameer Pujar
parent d2da4eb6b4
commit f7fafdc416

View File

@@ -1,7 +1,7 @@
/*
* tegra210_xbar_utils_alt.c - Tegra XBAR driver utils
*
* Copyright (c) 2017 NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -180,7 +180,8 @@ int tegra_xbar_put_value_enum(struct snd_kcontrol *kcontrol,
unsigned int change = 0, reg_idx = 0, value, *mask, bit_pos = 0;
unsigned int i, reg_count, reg_val = 0, update_idx = 0;
unsigned int reg[TEGRA_XBAR_UPDATE_MAX_REG];
struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG];
struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = {
{ NULL } };
/* initialize the reg_count and mask from soc_data */
reg_count = xbar->soc_data->reg_count;