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PCI: EPF: dma-test: Fix unaligned offset during dma reinit

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Clear the unaligned offset when reinitializing the DMA with new settings
to avoid CRC check fail.

Bug 4712065

Change-Id: I9faee6b5c74be32a421a594c8bb842d2b2cb97c2
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3163952
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
This commit is contained in:
Manikanta Maddireddy
2024-06-23 18:28:20 +00:00
committed by mobile promotions
parent 65900a51a9
commit fb5a616f92
1 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
include/linux/tegra-pcie-edma-test-common.h
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@@ -199,11 +199,6 @@ static int edmalib_common_test(struct edmalib_common *edma)
edma->edma_ch |= 0xFF;
}
/* FIXME This is causing crash for remote dma when BAR MMIO virt address is used. */
#if 0
epf_bar->wr_data[0].src_offset = 0;
epf_bar->wr_data[0].dst_offset = 0;
#endif
if (EDMA_CRC_TEST_EN) {
/* 4 channels in sync mode */
edma->edma_ch = (0x10000000 | 0xF0);
@@ -216,31 +211,36 @@ static int edmalib_common_test(struct edmalib_common *edma)
if (EDMA_UNALIGN_SRC_TEST_EN) {
/* 4 channels in sync mode */
edma->edma_ch = (0x02000000 | 0x10000000 | 0x10);
edma->edma_ch &= ~0xFF;
edma->edma_ch |= (0x02000000 | 0x10000000 | 0x10);
/* Single SZ_4K packet on each channel, so total SZ_16K of data */
edma->stress_count = 1;
edma->dma_size = SZ_4K;
edma->nents = nents = 4;
epf_bar->wr_data[0].size = edma->dma_size * edma->nents;
src_dma_addr += 11;
epf_bar->wr_data[0].dst_offset = 0;
epf_bar->wr_data[0].src_offset = 11;
}
if (EDMA_UNALIGN_DST_TEST_EN) {
/* 4 channels in sync mode */
edma->edma_ch = (0x01000000 | 0x10000000 | 0x10);
edma->edma_ch &= ~0xFF;
edma->edma_ch |= (0x01000000 | 0x10000000 | 0x10);
/* Single SZ_4K packet on each channel, so total SZ_16K of data */
edma->stress_count = 1;
edma->dma_size = SZ_4K;
edma->nents = nents = 4;
epf_bar->wr_data[0].size = edma->dma_size * edma->nents;
dst_dma_addr += 7;
epf_bar->wr_data[0].src_offset = 0;
epf_bar->wr_data[0].dst_offset = 7;
}
if (EDMA_UNALIGN_SRC_DST_TEST_EN) {
/* 4 channels in sync mode */
edma->edma_ch = (0x00800000 | 0x10000000 | 0x10);
edma->edma_ch &= ~0xFF;
edma->edma_ch |= (0x00800000 | 0x10000000 | 0x10);
/* Single SZ_4K packet on each channel, so total SZ_16K of data */
edma->stress_count = 1;
edma->dma_size = SZ_4K;
@@ -259,10 +259,10 @@ static int edmalib_common_test(struct edmalib_common *edma)
}
if (edma->cookie && edma->prev_edma_ch != edma->edma_ch) {
edma->st_as_ch = -1;
dev_info(edma->fdev, "edma_ch changed from 0x%x != 0x%x, deinit\n",
edma->prev_edma_ch, edma->edma_ch);
tegra_pcie_dma_deinit(&edma->cookie);
edma->st_as_ch = -1;
edma->cookie = NULL;
}