The perforce version of the MODS kernel driver
does not pull in any of the Tegra specific driver
functions. This prevents the perforce driver
from being compiled on any Tegra system or non
Tegra system with CONFIG_ARCH_TEGRA=y.
To allow the perforce driver to be compiled
replace CONFIG_ARCH_TEGRA with MODS_HAS_TEGRA
which is set based on CONFIG_ARCH_TEGRA in git
but left unset in perforce.
Bug 3397113
Signed-off-by: Lael Jones <lajones@nvidia.com>
Change-Id: Ie113d632c4dcc372058b9a1e3a549a70b8f7c03f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2607859
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Summary: Add debug fs to allow user to program
the error control registers in RAS so mods can
selectively disable errors if so desired. A
current example of this usecase is disabling
ras from throttling, which is thrown during
the mods Soctherm OC throttling test
Bug 200533168
Change-Id: Id9007e9e13ae9563ad2aae107b130bcd951f0bc4
Signed-off-by: Ellis Roberts <ellisr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224479
GVS: Gerrit_Virtual_Submit
Reviewed-by: Kiran Kasamsetty <kkasamsetty@nvidia.com>
Reviewed-by: Rohan Sreeram <rsreeram@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
TEGRA_DC_BLENDER_GEN2 configuration is enabled always if TEGRA_DC
configuration is enabled. And TEGRA_DC configuration is a must for
display to work. So TEGRA_DC_BLENDER_GEN2 ifdef is not needed and
can be safely removed to reduce ifdefs in display driver.
Change-Id: I4e1fde93d7b515a26bc6ce0b00915440dc30b13d
Signed-off-by: Ujwal Patel <ujwalp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1524810
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Due to implementation of SW formats which extend the display
color formats beyond 0xff, the format masks as well as the
byteswap masks have to be updated.
This change updates the following:
- Marks all SW defined formats as starting from 0x100
- Shifts all the byte swap masks to start at 0x10000
- Updates the SW and byte swap masks
- Updates the functions which classify yuv, planar and semi
planar formats
- Add the SW defined formats to the feature table listings
- Add SWAP_UV for vertical chroma subsampled formats
- Removes the SWAP UV flag
- Add sanity checks for SW defined formats in the kernel
Bug 1904472
Change-Id: I18f6cf69610e5bff206fa6b1336f63ee9a9a7424
Signed-off-by: Anshuman Kar <anshumank@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1517747
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add "sysfs" qualifier to existing API names for CRC to avoid
confusion with newly added tegra_dc_crc_* and tegra_nvdisp_crc_*
Bug 1858958
Change-Id: I9045ef494a0e56222d7d2555e19975f5f2bdbbeb
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1521973
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ujwal Patel <ujwalp@nvidia.com>
