BPMP-FW exposes the following MGBE RX clocks:
o mgbe0_rx_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_input_m [monitoring clk: virtual clk controls RX clk FMON]
o mgbe0_rx_pcs_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_pcs [mux between mgbe0_rx_pcs_input and mgbe0_tx_pcs]
o mgbe0_rx_pcs_m [monitoring clk: virtual clk controls RX PCS clk FMON]
To enable RX clock FMON -
o Issue clk_set_rate on MGBE_RX_INPUT and MGBE_RX_PCS_INPUT based
on UPHY GBE mode.
o Clk_enable already available on ToT for RX_INPUT_M
and RX_PCS_INPUT_M.
Bug 3288030
Change-Id: Ia71ccc9f21a5e79fecf149efae9032db25af60d8
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2544758
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
- On transmit complete callback
-- If OSI_TXDONE_CX_TS_DELAY flag is set in Tx done
flag, store buffer pointer along with pkt Id
in its internal array/list
- On Common interrupt:
-- Call osi to handle common interrupt.
- On trasmit complete interrupt:
-- Parse through internal array/list for pending TS
to read, by issuing OSI_CMD_GET_TS ioctl for pkt_id.
Loop until list is cleared or error is received.
-- On interface up
Remove old timestamp of channels initialized.
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Change-Id: I5104277de66dd240023f921fa5f7b4fcc035f74d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2535962
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
There are three clks for MGBE which needs to be set based
on UPHY GBE mode and PHY line rate.
o MGBE_MAC_DIV_CLK will be set based on PHY line rate
o MGBE_MAC_TX/TX_PCS clks will be set based on UPHY GBE mode
Below are the settings -
UPHY GBE mode = 10G:
===================
Possible MAC working rates: 10G/5G/2.5G
1) MAC DIVISOR: 312.5MHz, 312.5/2MHZ and 312.5/4MHz
2) TX CLK: 644.5MHZ
3) TX PCS_CLK: 156.5MHz
UPHY GBE mode = 5G:
==================
Possible MAC working rates: 5G/2.5G
1) MAC DIVISOR: 312.5/2MHz and 312.5/4MHz
2) TX CLK: 322.2MHZ
3) TX PCS_CLK: 78.125MHz
Bug 200739493
Change-Id: Ie6b21f87d2077b8be621a32b2034b4eff1eb391e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2541313
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Issue:
Observed multiple kernel warnings on page pool free,
due to invalid page pool handling.
Fix:
Fix per page pool creation in receive
DMA channel ring resources function.
Bug 200735979
Change-Id: Ic35f406bb4eab6282539349769ee9ae490b8cb93
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2537492
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Issue: Observed that VM interrupts continuously fired
if previous NAPI schedule not able to complete the
poll function. This case observed more frequently
if Tx coalescing enabled.
Fix: Disable VM interrupts whether NAPI scheduled
or not. Also uses IRQ-OFF variant for NAPI schedule
since IRQ's already masked.
Bug 200722499
Change-Id: If6fb694c43a1c11efb4f4b881b9fb08dec834917
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2537503
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Issue: For set_rx_mode() implementation, current design is creating
local list nodes with ATOMIC because this call in not in
Atomic context.
Fix: Use GFP_KERNEL flag to allocate memory for local list node.
Bug 200729431
Change-Id: I513ddce8a661ab6f465509791101e98c83bc8e96
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2527627
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Linux OSD code maintaining link list to identify L2
filter added/removed in compare to earlier list.
By doing this OSD sends address and dma channel which
should to be removed from hardware instead of full
list every time.
Bug 200711542
Bug 200711544
Bug 200713215
Change-Id: I95d4dc687c5fd45a6e0bbc3c097e59b90b03b0e5
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2519592
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Issue:
1) Missing support for packet MC/BC packet duplication
2) Remove MAC UC and BC address on ether_close()
Fix:
1) Update OSI_CMD_L2_FILTER structure parameter to support
new algorithm.
2) MAC UC and BC address added to filter from ether_open()
and ether_resume() function.
3) Configure MAC register to support MC/BC packet
duplication
Bug 200711542
Bug 200711544
Bug 200713215
Change-Id: Ie589892de121e5873f5dfa9b9db9bf5c441ece71
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2519591
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
To reduce number of external OSI interface APIs,
consolidated all IOCTL API to one interface API.
OSD should use same for all interaction to OSI.
Bug 200671160
Change-Id: I2ada2746f29be6cf396709c2ec12dd96d4a5ca15
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
This commit adds the driver interface for the
MACsec controller. The driver interface is
invoked using generic netlink messages from
userspace MACsec key agreement agent.
Currently sysfs node is added to check the irq
stats for default macsec controller operation.
Bug 2913560
Change-Id: I07b0b778ba1c6674e87b103a3e68e158fea61c2c
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
- Add a new DT node to enable Multiple DMA routing
for netdev MC MAC ddress. Read the DT value
and store it into OSI core private data.
- Add new driver private IOCTL for MC DMA channels
selection as inputs and call ether_set_rx_mode
to update MAC filters with given DMA channels route.
Bug 200565911
Change-Id: I1e65322489e34c4b6318a769dac963073d4887ad
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
- Define new "nvidia,ptp_rx_queue" DT node entry
- Read "nvidia,ptp_rx_queue" DT node value into
osi_core->ptp_config.ptp_rx_queue. On no DT
entry case set this value to "osi_core->mtl_queues[0]"
- Validate "osi_core->ptp_config.ptp_rx_queue" value
with "osi_core->mtl_queues" array values. If no match
found give error and set this value to
"osi_core->mtl_queues[0]"
- Add new private IOCTL command to call OSI RX route API.
Bug 200596985
Change-Id: I2c05d4c6f3f4207d9efd6b6777d29fe2409de1a3
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2312295
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
