Tx frame count and software timer based interrupt coalescing
is enabled. Tx frame count based interrupt coalescing can be
enabled only when tx software timer based interrupt coalescing
is also enabled.
Bug 200529168
Change-Id: I8ac701c86238e8d34d7dbe9924df1162083c023e
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2234610
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Issue: ether_get_ptptime() is registered as a callback
function to read ptp time using tegra_register_hwtime_source.
But it is not unregistered before interface is brought down.
This causes clients to still query for timestamp even though
interface is down and MAC is in reset, resulting in CBB errors.
Fix: Unregister the callback function in ether_close()
Bug 200556936
Change-Id: Idb5b698460f02101c931fd64fbdfc9c06949e05a
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210705
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Issue:
1) Spin locks are used for code path which is already serialized
by network stack
2) On interface down/up, MAC registers are getting reset and
re-initialized but private structure variables are not updated
Fix:
1) Remove spinlocks
2) Re-initialize private structure variables
Bug 200548252
Bug 200547544
Change-Id: Ifb0ce27ba96f8657eebde21e5d02d8b36fb1778b
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189974
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HW MMC registers are 32 bits in size. Some of these will
overrun in few secs if there are live traffic at line rate.
Scheduling work queue to get periodic value from MMC
HW registers and update in 64 bits local variables, will
be solution to this HW limitation.
Bug 200544686
Change-Id: Ifc358f3f6b50839f7d9f48c2f98cb2cdd9ac0821
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2179298
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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Issue: During system suspend, PHY framework is trying to
access the PHY registers even though the ethernet interface
is not up which inturn causing the bus errors since MAC clocks
not enabled.
Fix: Add MAC clocks enable check before accessing the PHY
registers through MDIO bus.
Bug 200548320
Change-Id: Ic85ae82bbc7e7f33203cc94f8407bdfd23f75502
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2187285
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1) Register broadcasting MAC timestamp to clients so that
client can make use of the ptp callback for getting the
timestamp
2) Add private ioctl to read Timestamp information of
both HW PTP time and kernel time
Bug 200512422
Change-Id: I03509cc02f28571108a1061c739840c86f960af4
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161172
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Issue:
1) MTL Queue can be in any order in input to DT. If not
initialized sw can crash.
2) Don't use return value of skb_get_queue_mapping as
channel number.
Fix:
1) As MTL Queue sequence is already read, use it for
initialization and storing corresponding configuration.
2) Derive the channel number based on the q index
provided by skb_get_queue_mapping.
Bug 200512422
Change-Id: I145f67ee07101ae69821b5ae4a770e512252985b
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156243
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Issue: Configure Max MTU size support for specific platform
Fix:
if "nvidia,max_platform_mtu" present in platform DT and less than
MAX_HW_MTU supported
set platform max value from DT
else
default MTU(1500 bytes) will be used as platform max mtu
Bug 2594873
Change-Id: Id9b912a0c797c8cefb4233209b4d38004bcdf840
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137919
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Updated IOCTL path to not get impacted with new API
change. OSI call should be done with correct parameters
1) dma_routing_enable
2) dma_chan and
3) addr_mask (for L2 filtering) to support new IOCTL
4) src_dest (for L2 filtering) to support new IOCTL
Included logic for User priority based RxQ selection. We can have DT
entry "nvidia,rx_queue_prio" to configure this setting
i.e. for valid following Queue mapping
Priorities 6,3 to Queue 3
Priorities 4,5 to Queue 2
Priority 0 to Queue 1 and
Priority 1 to Queue 0.
setting will be nvidia,rx-queue-prio = <0x2 0x1 0x30 0x48>;
If static channel selection, i.e. RXQtoDMA set with value 0x03020100,
Priorities 6,3 to Queue 3 to chan 3
Priorities 4,5 to Queue 2 to chan 2
Priority 0 to Queue 1 to chan 1 and
Priority 1 to Queue 0 to chan 0
else if DCS(dma channel selection) enabled
channel will be selected based on filter rules.
Included logic to take input from User On DCS enable or disable. User can
update dt entry "nvidia,dcs-enable", for dcs enable disable for all queue.
i.e nvidia,dcs-enable = <0x1> will enable DCS for all queue.
Bug 200525721
Change-Id: I4ba820f178b03424d01bb4ddd1f1d6eadde572f7
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133196
GVS: Gerrit_Virtual_Submit
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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These stats are read from MAC HW RMON counters as well as SW controlled
control from Core and DMA path.
ethtool -S <interface> is used to get statistics.
There are 3 stats
1) ether_mmc_counters: EQOS HW counters
2) ether_xtra_stat_counters: SW counters from osi/core
3) ether_xtra_dma_stat_counters: SW counters from osi/dma
Bug 200519211
Change-Id: I5b1b6592541c650f01e845667eca2f5c59bcfd08
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113962
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Ethernet pad calibration needs to be triggered for temperature
changes in steps of 35C from -40C to 110C. In order to get
indication of current operating temperature, register a ethernet
cooling device with thermal zones defined as per above requirement.
When the temperature trips these zones, callback function is invoked
from kernel thermal framework, and ethernet driver can trigger pad
calibration.
Bug 1679250
Change-Id: Iaeccca650e371843fa571f7b368bb5464e106314
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120431
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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1. ARP offload can be configured via private ioctl.
Application requesting the arp offload configuration
should provide the IP address to be configured for
ARP offload via ioctl data struct. Refer to
struct ether_ifr_data and
struct arp_offload_param for details.
2. Tx/Rx Checksum offload can be configured via ethtool
3. TCP Segmentation offload can be configured via ethtool
Bug 2571001
Change-Id: If639ab9049db97f200911af456ddb8cb8433fa12
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109676
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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Add dma-mask parsing in device tree for eqos
driver if IOMMU is enabled. This will allow
memory allocations from the specified address
and downwards, while device can reach every part
of physical memory through the IOMMU.
dma-mask will be remain default 32-bit mask if no
IOMMU is present since now DMA mask represents a
fundamental limit of the device.
Bug 200458098
Change-Id: I6eef70f97dba5807d6483cbd76e474d321debe75
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096023
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1) support for driver probe based on nveqos
2) support for EQOS hw init
3) data transmission support for Tx and Rx
Bug 200507585
Change-Id: I5c8bc88f97b2e61a2b346a23aadcb19a7b8c53a5
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
