Issue:
To save more power PHY RXC will be disabled when PHY in LPI state by
setting 10th bit in below register. This is standard PHY register.
- PCS Control 1 register (MMD device 3, Address 0x00)
When EEE enabled above register being programmed (10th bit got set) and
it created issue while accessing the MAC registers through indirect
addressing since RXC stopped from PHY.
Fix:
Don't stop RXC in LPI for Orin EQOS
Bug 200776300
Bug 200765092
Change-Id: I4150eebe8e2a5ab79ad5b7180232adad2331e315
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2599137
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Issue:
- TX packet fragments are not working
on Orin platform.
- Express packets pass through even time
interval is not sufficient to send packet
Fix:
- Set OSI_PKT_CX_LEN and tx_pkt_cx->payload_len
for non TSO packet. this will update frame
length in TDECS3
Bug 200765943
Bug 200763256
Change-Id: I82cc91e176d9ac84d654ef7f60686ebc4024d3da
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2592048
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Issue: SID needs to be programmed through HV window
to get it reflected in controller register space.
Currently its programmed through RM window.
Fix: Get HV window base address from DT and program
in controller registers in non-hypervisor mode.
Store MAC instance ID to program the same ASID
values which are used in DT.
Bug 200761024
Change-Id: Ie9bcaebcba39f2d07438c9502591c0f51f22378f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2592481
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Issue: MGBE supports upto 16K jumbo size.
There is enough MTL queue space also
for 16K packet even with all 10 queues
enabled in MGBE. So no need to restrict
> 9k jumbo to single channel config only.
FIx: For MGBE, unconditionally allow upto 16K
jumbo size setting.
Bug 200760072
Change-Id: I734ce3be13605e4db992a1679e2de0736bd2583f
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2579108
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Issue
- Driver probe defer causes failed prints on kernel boot logs
if clk/reset controller driver module is not initialized
before nvethernet module probe.
Fix
- The probe defer is part of kernel mechanism to retry module
initialization and hardware setup. This is not an error
or failure for software driver.
Only in case of probe failure, throw error logs in console
Bug 200728771
Bug 200732811
Change-Id: I9c421db6ceedc108553f9f2b33f4f3993d63c02f
Signed-off-by: Sushil Singh <sushilkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2563340
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
ifr_data pointer value used to carry mii_ioctl_data from
user space to kernel space. When all values are zero it
reflects the pointer value as zero and ifr_data NULL pointer
check will result in failure.
Driver should not check since ifr_data pointer value itself
represent mii_ioctl_data. So removing the NULL check for ifr_data.
Bug 200733774
Change-Id: Ibf405fe22c3e2e694e08eac598e9431066703c3c
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2564428
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Algorithm:
- There is one master queue and one final queue to maintain the
packets.
- Final queue will start when a packet received with TTL=1
- TTL = 2 and 3 packets will be queued into final if those are in
sequence else those will be queued to master queue.
- When packet received with TTL = 2 then only merge process will start
- For every valid final queue merge starts by looking at the IPID
in master queue in increment order. This loop continues until
TTL = 2 found in master queue.
- Once TTL = 2 found then entire final queue will be given GRO
layer in sequential order.
Bug 3106903
Change-Id: I6cc08f3faae67a04813d32d59f7cce02f06dccbf
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2554423
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
BPMP-FW exposes the following MGBE RX clocks:
o mgbe0_rx_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_input_m [monitoring clk: virtual clk controls RX clk FMON]
o mgbe0_rx_pcs_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_pcs [mux between mgbe0_rx_pcs_input and mgbe0_tx_pcs]
o mgbe0_rx_pcs_m [monitoring clk: virtual clk controls RX PCS clk FMON]
To enable RX clock FMON -
o Issue clk_set_rate on MGBE_RX_INPUT and MGBE_RX_PCS_INPUT based
on UPHY GBE mode.
o Clk_enable already available on ToT for RX_INPUT_M
and RX_PCS_INPUT_M.
Bug 3288030
Change-Id: Ia71ccc9f21a5e79fecf149efae9032db25af60d8
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2544758
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
- On transmit complete callback
-- If OSI_TXDONE_CX_TS_DELAY flag is set in Tx done
flag, store buffer pointer along with pkt Id
in its internal array/list
- On Common interrupt:
-- Call osi to handle common interrupt.
- On trasmit complete interrupt:
-- Parse through internal array/list for pending TS
to read, by issuing OSI_CMD_GET_TS ioctl for pkt_id.
Loop until list is cleared or error is received.
-- On interface up
Remove old timestamp of channels initialized.
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Change-Id: I5104277de66dd240023f921fa5f7b4fcc035f74d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2535962
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
There are three clks for MGBE which needs to be set based
on UPHY GBE mode and PHY line rate.
o MGBE_MAC_DIV_CLK will be set based on PHY line rate
o MGBE_MAC_TX/TX_PCS clks will be set based on UPHY GBE mode
Below are the settings -
UPHY GBE mode = 10G:
===================
Possible MAC working rates: 10G/5G/2.5G
1) MAC DIVISOR: 312.5MHz, 312.5/2MHZ and 312.5/4MHz
2) TX CLK: 644.5MHZ
3) TX PCS_CLK: 156.5MHz
UPHY GBE mode = 5G:
==================
Possible MAC working rates: 5G/2.5G
1) MAC DIVISOR: 312.5/2MHz and 312.5/4MHz
2) TX CLK: 322.2MHZ
3) TX PCS_CLK: 78.125MHz
Bug 200739493
Change-Id: Ie6b21f87d2077b8be621a32b2034b4eff1eb391e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2541313
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Issue:
Observed multiple kernel warnings on page pool free,
due to invalid page pool handling.
Fix:
Fix per page pool creation in receive
DMA channel ring resources function.
Bug 200735979
Change-Id: Ic35f406bb4eab6282539349769ee9ae490b8cb93
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2537492
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Issue: Observed that VM interrupts continuously fired
if previous NAPI schedule not able to complete the
poll function. This case observed more frequently
if Tx coalescing enabled.
Fix: Disable VM interrupts whether NAPI scheduled
or not. Also uses IRQ-OFF variant for NAPI schedule
since IRQ's already masked.
Bug 200722499
Change-Id: If6fb694c43a1c11efb4f4b881b9fb08dec834917
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2537503
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
