Add a few microseconds delay between IVC channel reset retries.
This prevents kernel logs from flooding if dce bootstrapping takes
some time for any reason.
Based on logs below, DCE is taking around 10-30 microsecond for channel reset.
So, Keeping the delay of 10-20 microseconds.
20:26:46.637409: dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x5]
20:26:46.637421: message repeated 15 times: [ dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x5]]
---
20:26:46.637429: dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x1]
20:26:46.637458: message repeated 12 times: [ dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x1]]
----
20:26:46.637461: dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x2]
20:26:46.637471: message repeated 15 times: [ dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x2]]
Jira TDS-6381
Change-Id: I0f8d3c55058019df5a52edd232eae93b3bf84276
Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3304216
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
- dce-client-ipc.c is a common file used by HVRTOS as well to
register as a DCE client.
- We need to refactor existing register function due to certain
HVRTOS restrictions at init time.
1) Register function will be called at init time from HVRTOS.
2) HVRTOS doesn't allow any mutex acquire calls or wait calls
during INIT phase.
JIRA TDS-16581
Change-Id: I1b3a9587c1e237c2cca8214a3acce9ff34d98cc0
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3280251
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
- This is a follow-up CL to address a comment in
I55594d8e34c3b572129119d1f7240cde76cf37bd
- This change will remove below simple static wrappers
from dce-ipc.c and directly call the corresponding OS functions.
- _dce_ipc_get_next_write_buff()
- _dce_ipc_get_next_read_buff()
JIRA TDS-16126
Change-Id: Ie8c08ace75f3c6e14e803c6aeccdf43a0c27f3fa
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3257965
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
- Abstract out iosys_* dependencies for writing/reading to/from
message header and memcpy to os specific implementation.
- Add new dce-os-ipc.c
- Cannot add these functions to existing 'dce-os-ivc.h' as
static inline functions because these functions access
dce_ipc_channel defined in dce_ipc.h.
- Cannot include dce_ipc.h to this file as it creates
a circular dependency.
- Also fix exsisting issue of not defining 'tegra_dce' inside
dce-ipc.h
- This is exposed now because we're including dce-ipc.h to
dce-os-ipc.c which doesn't include any prior headers which
define tegra_dce.
- Fix by doing forward define to avoid circular dependency
with dce.h
- Additionally fix below iosys issues:
1) Change Iabebef33719c38a8aa4db8573a0dd7dd7e5f83f6 introduced
an issue because NV_TEGRA_IVC_STRUCT_HAS_IOSYS_MAP demands
different prototypes for below functions:
- dce_os_ivc_get_next_write_frame()
- dce_os_ivc_get_next_read_frame()
2) Now since dce_ipc_is_data_available() uses
dce_os_ivc_get_next_read_frame(), it needs to define
frame with iosys_map for IOSYS Linux 6.2 usecase. So need
to creata a OS abstraction for this too.
JIRA TDS-16126
Change-Id: I55594d8e34c3b572129119d1f7240cde76cf37bd
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3233117
Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Module covered: dce-trace
This is not a functional change. It does the following:
1) Add new os/linux/include/dce-os-trace.h to abstract
trace event functionality. Define static inline
wrappers dce_os_trace_*() to corresponding existing
trace_*() functions.
2) Remove intermediate os header os/include/os-dce-events.h
and replace all includes directly with <dce-os-trace.h>`
JIRA TDS-16126
Change-Id: I800be4a2b9b51214af4c2531e34dbdd41caccaea
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3229379
Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Modules covered in this CL: dce-os-ivc
This is not a functional CL. It does the following:
1) Move os/include/linux-kmd/os-ivc.h to
os/linux/include/dce-os-ivc.h
2) s/os_ivc/dce_os_ivc/g
3) Delete old intermediate header os/include/os-ivc.h and include
<dce-os-ivc.h> directly.
JIRA TDS-16126
Change-Id: Ib6264a39910dbb4a107fd2261005c5e593b4b9b7
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3228545
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com>
Modules covered in this CL: dce-lock
This is not a function CL. It does the following:
1) Move dce-lock.h to os/linux/include/dce-os-lock.h
2) s/dce_mutex/dce_os_mutex/g
3) Remove intermediate includes previously introduced:
a) Delete os/include/os-lock.h
JIRA TDS-16126
Change-Id: I994bcbf75ec87461c0dc2714b300d0ad1e3ee018
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3228541
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Modules covered in this CL:
1) dce-os-log
This is not a functional CL. It does the following:
1) Rename dce_<info/err/debug/warn> to
dce_os_<info/err/debug/warn>
2) Rename dce_log_msg() to dce_os_log_msg()
3) Rename DCE_<WARNING/ERROR/INFO/DEBUG> to
DCE_OS_<WARNING/ERROR/INFO/DEBUG>
4) Move dce-log.h to os/linux/include/dce-os-log.h
5) Stop using old abstraction:
a) Replace <os-dce-log.h> includes with <dce-os-log.h>
6) Delete all related old deprecated log files:
a) os/include/linux-kmd/os-dce-log.h
b) os/include/os-dce-log.h
JIRA TDS-16126
Change-Id: I75ebe98a785c298678d80371184efae6e46932ee
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3228536
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
- Move IPC region alloc/free calls to OS layer because
they mean different for different OSs.
- For Linux it will allocate/dma map memory for IVC comm.
- For HVRTOS it will simply fetch pre-allocated memory details
since the memory allocation is only allowed in hypervisor module.
- Accordingly, rename the API dce_ipc_allocate_region() ->
dce_ipc_init_region_info(). Similarly for free as well.
JIRA TDS-16052
Change-Id: I201cb5b1bc7384a9b0ccdbf5bc72bbd78d6b1506
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3180405
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Instead of relying on kernel version to determine if the 'tegra_ivc'
structure has a member that is of type 'struct iosys_map', add a compile
time test to the conftest.sh script to determine this at compile time
for the kernel being used. This is beneficial for working with 3rd party
Linux kernels that may have back-ported upstream changes into their
kernel and so the kernel version checks do not work.
Bug 4119327
Change-Id: Ia993ca9df7694347252a795c7dee1e95f2f9fa2f
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2985743
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
The current code doesn't notify DCE IPC after DCE IPC is in ACK state
Current Flow:
CPU DCE
1: tegra_ivc_init ---------
2: DCE_ADMIN_CMD_IPC_CREATE tegra_ivc_init
3: --------- tegra_ivc_channel_reset
dce:SIVC_STATE_SYNC
cpu:ESTABLISHED
4: tegra_ivc_reset
dce:SIVC_STATE_SYNC ---------
cpu:SYNC
5: Notify() tegra_ivc_channel_notified
dce:SIVC_STATE_ACK
cpu:SYNC
6: tegra_ivc_notified ---------
dce:SIVC_STATE_ACK
cpu:ESTABLISHED
After Step 6 DCE state is in ACK state and CPU state is in ESTABLISHED
state. As there is no further cpu->dce notification in RM_NOTIFY
channel, dce state stays in the "ACK" state and any attempt to send msg
on RM_NOTIFY channel from dce->cpu fails.
This patch notifies dce after step-6, So dce channel is also in the
"ESTABLISHED" state.
If steps 3-6 get executed in CPU before Step 5 in DCE gets a chance
to execute (DCE is slow), the CPU IPC state will change to "established".
Now when step 5 will execute in DCE, it'll see the CPU state as
"established" so, It'll make the DCE state also "established".
That's how it's working today.
Bug 3861985
Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com>
Change-Id: Ieb13f525d3f81b30aaae848d8d5adb1106856b65
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2840065
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
While MST is used, We get two async msgs from DCE and schedule 2 worker
threads, But during processing (dce_client_process_event_ipc) of these
messages, We are processing all the pending messages in one go. So,
while the second worker thread is scheduled, there is no new message
to read.
This Patch fixes the loop to try reading only when there is a new msg to
read. Also convert info print to debug, to avoid print noise.
Bug 3801736
Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com>
Change-Id: Iddf9ea8f0194539baa8c52616e2f836527400176
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2810440
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- when there are multiple async events back to back from DCE with very
short time gap between 2 events(for example, in case of DP MST,
2 heads could be sending flip event notification back to back at
almost same time), there is a possibility of 2nd async event getting
processed very late when shared mailbox register is set to zero as part
of processing 1st async event and before processing of 2nd async event.
- current change fixes it by processing all pending IVC frames for IPC
channel when processing an async event.
- change few error logs to info logs as these are not actually errors.
Bug 3582863
Bug 3429668
Change-Id: I29b1813bed50c4583e37f02bf656802081ccf9d3
Signed-off-by: Santosh Reddy Galma <galmar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2698560
(cherry picked from commit dd1abfa6eaab6e4f599d8c97bdccc7cbb67e1341)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2700438
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
GVS: Gerrit_Virtual_Submit
Re-organize IPC channel reset and mailbox interrupt handling code to
fix race condition where KMD was receiving new msg from DCE while
processing previous msg and clearing mailbox interrupt as part of it.
which was causing wait_for_ipc to get stuck.
JIRA TDS-6381
Change-Id: Ibd6ab1758d9b5b2e3709a03dadbc84f2585653a4
Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2460641
Reviewed-by: Santosh Galma <galmar@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
For T23x, we have a separate R5 based cluster
named as Display Controller Engine(DCE) to run
our Display RM code. This driver will run on CPU
with the following functionality:
Via debugfs for test and bring-up purposes:
1. Reads the DCE firmware image into DRAM.
2. Sets up DCE AST to cover the DCE firmware image.
3. Sets up R5 reset vector to point to DCE firmware
entry point
4. Brings DCE out of reset
5. Dumps various regsiters for debug
In production env:
1. Manages interrupts to CPU from DCE
2. Uses bootstrap command interface to define Admin
IPC
3. Locks down bootstrap command interface
4. Uses Admin IPC to define message IPC
5. Uses Admin IPC to define message IPC payload area
6. Uses Admin IPC to set IPC channels
6. Uses Admin IPC to define crashdump area
(optional)
7. Provides IPC interfaces for any DCE Client running
on CCPLEX including Display RM.
8. Uses Admin IPC to set logging level (optional)
This patch puts a framework in place with the
following features :
1. Firmware Loading
2. AST Configuration
3. DCE Reset with EVP Programming
4. Logging Infra
5. Debugfs Support
6. Interrupt Handling
7. Mailbox Programming
8. IPC Programming
9. DCE Client Interface
10. Ftrace Support for debug purposes
Change-Id: Idd28cd9254706c7313f531fcadaa7024a5b344e7
Signed-off-by: Arun Swain <arswain@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2289865
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com>
Reviewed-by: Santosh Galma <galmar@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Mahesh Kumar <mahkumar@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
