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Author SHA1 Message Date
Revanth Kumar Uppala
e997938c0e Revert "r8168: Enable CONFIG_SOC_LAN" 
This reverts commit c63de1c5e2c16fabccfd21ac858693438e8bb427.

Reason for revert: Throughput reduced with this change

Change-Id: Ie2293f9cedd9b00c28f1ce08c24dbee68674dde9
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3232362
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
 2025-07-24 10:19:10 +00:00
Akhil R
84e4d456fa i2c: tegra-slave: Support 10-bit addressing 
Support 10-bit addressing in Tegra I2C slave mode

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Change-Id: I199e636d7c8058cd3d4ae83abcfd48cfa02febf2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3233634
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-07-24 10:19:10 +00:00
omar
79633ca404 drivers: pva: add fence update method 
Fence update method is defined as increment or set.
when method ios set, the fence value is set to the value
requested.

This applies only to semaphores.

Bug

Change-Id: I1c744826868dde7950c9482ae9a0c601e63a63a1
Signed-off-by: omar <onemri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3231374
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ashwin Rao <ashwinr@nvidia.com>
Tested-by: Ashwin Rao <ashwinr@nvidia.com>
Reviewed-by: Sreehari Mohan <sreeharim@nvidia.com>
Tested-by: Sreehari Mohan <sreeharim@nvidia.com>
 2025-07-24 10:19:10 +00:00
Paritosh Dixit
af52a2b6c0 nvidia-oot: Add .gitignore 
Add .gitignore so that git status does not show build artifacts.

Bug 4814000

Change-Id: Iae3ef2be2107db92350038131628903c12b1f1c7
Signed-off-by: Paritosh Dixit <paritoshd@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3240531
(cherry picked from commit 696fd39c49)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3241033
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
 2025-07-24 10:19:10 +00:00
Khushi
e57f71b4d0 vse : GCSE1/2 AES Linux 
Added engine id in linux vse driver for GCSE1/2 AES0/1
Jira ESSS-1413

Change-Id: Icb38941c2c17e04fe0979070c80abaac9d018e74
Signed-off-by: Rounak Agarwal <rounaka@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3168936
Tested-by: Khushi . <khushi@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Reviewed-by: Leo Chiu <lchiu@nvidia.com>
 2025-07-24 10:19:10 +00:00
Mahesh Patil
a1291a7323 nvethernet: Set the mac clk rate in driver 
1) Setting mac clk rate correctly in driver
2) Set speed correctly if phy_iface_mode set to USX-5G/USX-10G
3) Set the mgbe/eqos rx clocks during interface up

Bug 4874956
Bug 4872381
Bug 4745869

Change-Id: Ie3c39f44b713661e10a4fb20090c26d09667beea
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3216075
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-07-24 10:19:10 +00:00
Praveen James
2d1629804e fsicom: update hsp mb assignment to fsi core 
Hsp mb for fsicom notifications are
assigned to configured fsi notification
core in sequence.

Bug 4825460
Jira FSIS-565

Change-Id: I9365f7c8c6459ad749f6fbf0a0dd9775b4225822
Signed-off-by: Praveen James <pjames@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3204135
(cherry picked from commit b0b1e5cbbf888a558aedd563d81057301ee4ac8a)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3206769
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Kovid Kumar <kovidk@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3217463
 2025-07-24 10:19:10 +00:00
Praveen James
55847ce7a0 fsicom: Add support for fsi core2 and core3 
fsicom driver updated to support fsicom
channels without notification. With notification
disabled channels fsicom can support all four
cores of FSI

Bug 4805453
DOS-SHR-10636

Change-Id: I6cf4dd36c1570505dbcf582499189bd974ed095f
Signed-off-by: Praveen James <pjames@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3197598
(cherry picked from commit 1dbdf63d67b102908c845671d18ddf4d14ae498f)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3206768
Reviewed-by: Kovid Kumar <kovidk@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3217458
 2025-07-24 10:19:10 +00:00
Janardhan Reddy
1fb5a4f931 nvscic2c-pcie: Fix edma error reporting issue 
pci_client abstraction supports notification to application.
Each endpoint has to register with pci_client for notification which
return link_event_id after registration.
link_event_id is index in lookup table with total size as MAX_ENDPOINT.
This link_event_id is allocated sequential and does not match with ep_id
which is endpoint index with max as MAX_ENDPOINT.

stream-extension is not aware about link_event_id and uses ep_id for
notification which leads to mismatch in look up table finally dropping
notification.

Registering for link event in sequential manner does not help much as
registration against ep_id will make lookup table and endpoint database
one-to-one mapping.

Update endpoint registration for link event based on ep_id and use ep_id
in lookup table for notification purpose.

Bug 4913236

Change-Id: I75bfdbf0e8e5b7b11b0cca7dc266f01f492362f6
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3233789
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Tested-by: Janardhan Reddy AnnapuReddy <jreddya@nvidia.com>
 2025-07-24 10:19:10 +00:00
Srishti Goel
9c40df022c PCI: endpoint: Add DMA sanity test function driver 
Added a sanity DMA testing driver which submits 2 descriptors of 0.5MB,
2.5MB and 6.25MB each. Repeats this 10 times and captures the perf,
bit-transfer errors and time taken.

Bug 4865361

Change-Id: Ibda3d55d848c918bb3b97412b0cbb33b0a460f6e
Signed-off-by: Srishti Goel <srgoel@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3220195
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-07-24 10:19:10 +00:00
Srishti Goel
05ad3c46c6 misc: Add EP client DMA sanity test driver 
Added a DMA EPC testing driver which submits 2 descriptors of 0.5MB,
2.5MB, and 6.25MB each. Repeats this 10 times and captures the perf,
bit-transfer errors and time-taken.

Bug 4865361

Change-Id: I56c63a983e4ff4f45adc77fb89e9fe0f77b36bcd
Signed-off-by: Srishti Goel <srgoel@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3221078
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-07-24 10:19:10 +00:00
Srishti Goel
556ee3c643 linux: Add PCIe DMA sanity header 
Add common DMA sanity helper header that can be used by both EP client
and EP function sanity DMA test drivers.

Bug 4865361

Change-Id: Ia448065a694e3784b5bd158ebb8a9b049c1fa62c
Signed-off-by: Srishti Goel <srgoel@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3225560
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-07-24 10:19:10 +00:00
Sanath Kumar Gampa
9d5d4f6e37 NvEthernet: Addition of common OSI MACSec file 
Reorged OSI MACSec and added a common MACSec OSI file

Bug 4874880

Change-Id: Ib6db144b5df271ab6b82f707f8813d1a7ed79455
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3214901
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
 2025-07-24 10:19:10 +00:00
Sanath Kumar Gampa
6ca5a03728 nvethernet: Add MACSec counters to ethtool stats 
Bug 4915922

Change-Id: I21920fe788d8a3789faeaa13a82d6961ee1371a4
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3233767
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2025-07-24 10:19:10 +00:00
Surbhi Singh
a47c3ef56d video: tegra: nvmap: Fix INT08-C using overflow.h 
JIRA: TMM-5724
Bug 4479044

Change-Id: I72fd476edf686a2154a8976fdeb4a686a24ddbb8
Signed-off-by: Surbhi Singh <surbhis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3233433
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2025-07-24 10:19:10 +00:00
Ketan Patil
44a095795e video: tegra: nvmap: Move relevant code to respective units 
- Move the code from nvmap_priv.h to relevant units.
- Delete nvmap_priv.h

JIRA TMM-5751

Change-Id: Ic0df459fb9db0714a1b2a65b463fae8adbbc49f1
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3232636
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2025-07-24 10:19:10 +00:00
Pritesh Raithatha
cfda55996f video: tegra: nvmap: move dmabuf code to dmabuf unit 
Move dmabuf code to dmabuf unit. This will help to deprecate
nvmap_priv.h.

JIRA TMM-5721

Change-Id: I5fc2a6e0d8ff1939df5e5623fc9d12fa3592e3bd
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3234588
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2025-07-24 10:19:10 +00:00
Surbhi Singh
c79fe58101 video: tegra: nvmap: Fix INT08-C using overflow.h 
- pend-pstart may wrap, hence using check_sub_overflow.

JIRA: TMM-5724

Bug 4479044

Change-Id: I0214a453919ab6d789811b3cb02525d3c78b7932
Signed-off-by: Surbhi Singh <surbhis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3232443
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
 2025-07-24 10:19:10 +00:00
snchen
28668cde01 vi5: camera: add ovrride capture timeout control 
add CID to override the capture timeout.

bug 4737219

Change-Id: I6df8e760ce8051054ba34a8b85b00bb237f9cd98
Signed-off-by: snchen <snchen@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3173821
(cherry picked from commit 20374db85d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3196700
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2025-07-24 10:19:10 +00:00
Laxman Dewangan
267eedc25d ufs: Add conftest to check UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE 
Not all kernel define the enum UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE

Add conftest to find out whether kernel has define the enum
UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE or not and then check for macro
before using it.

Bug 4911768

Change-Id: I4eba6f02ab79c1d4a5bdefb3ec831cc4ae34d527
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
ac4e44ec34 scsi: ufs: Assert before de-assert 
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I8c11d202b20fd90320dae510e3da2193a1d8dfdf
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
24e024444b scsi: ufs: check for go bit status 
GO bit will be cleared after driver
writing it to 1. Need to check the
clear status. Added check for the same.

Bug 4782274

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I71f035a27fb95de3e37d515a34c48c493f827a44
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
e86ab401cc add delay after hdiv 
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I357dd071ad76dc81d16810f8b5f0e44cf42fa8a3
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
f66b44645e scsi: ufs: Set pll3 rate_b 
Set PLL3 RATEB rate as 582400000.

Bug 4757621

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I18652261b7224d162a502de3d30e5eb354fd6675
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
fb95615c17 ufs: Remove rx calibration 
Removed rx calibration in resume.

Change-Id: Ib7eb0c306cb1f424b4dca707e39e70f2a42fe4e0
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
701657e6f7 ufs: Set utmi_pll1 as parent for cpu_isc clocks 
Set utmi_pll1 as parent for cpu_isc clocks

Bug 4782274

Change-Id: Iab71527dc6de3f46d4b7880c3dd00eadc130c5ba
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
711b5110fc scsi: ufs: Enable quirks for power sequence change 
Change-Id: I658e6b56cd05cb366a6ae3d277d05fb97a663f6a
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
179dc474f7 ufs: scsi: enable lane1 rx calibration first 
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I549a15b2853c1b890aec7e66c5296d56b8616f25
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
0b489f8588 ufs: Do not disable clocks in suspend 
Do not disable clocks in suepend.

Bug 4732470

Change-Id: Iabf05c1d80e3339c10f7824edcc333cef065bc33
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
14d246d8a3 scsi: ufs: Remove dev_err for information prints 
dev_err is used for information prints.
Changed them to dev_info and dev_dbg.

Bug 4736849

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I990edef75566ca718fab611b36385f6ec5f12c44
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
c3d33b827c ufs: Enable ufs for RDL fix parts only 
Read fuse to check if chip has RDL fix or not.
Return error for non-RDL chips.

Bug 4243018

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: Ibe441ca136c18e03cebbc1cd5d0cc529d45005c6
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
347e5727ac ufs: Fix ufs crash 
Change-Id: I4d266fa940ce3428cc57805ada917f7f42d0ed32
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
66e8bf380a ufs: ufs clock change to use ufs_cg_sys_div 
Change-Id: I3d79d442fb10cbfc3d2e4e8d8803190dce839c93
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
e318d3196c scsi: ufs: Do not enable pllrefe clk in T264 
pllrefe is not used in T264 ufs. Do not enable it.

Bug 4199271

Change-Id: I0d940b66e1a30ac2b097c07a1ba470ddc2f41de4
 2025-07-24 10:19:10 +00:00
Mallikarjun Kasoju
5ed0a15b2d scsi: ufs: Corrected ufs parent clock name 
Corrected ufs parent clock name.

Bug 4199271

Change-Id: I528d32f246ec6f6167e7895b8bec30b1f6c959b1
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
 2025-07-24 10:19:09 +00:00
Mallikarjun Kasoju
f869389dfc ufs: Corrected ufs parent clock 
UFS parent clock in T264 is pllrefufs_clkout624
and the rate is to 208 MHz.

Bug 4199271

Change-Id: I5b86e199f93fc1c81506cb29391b96efdc7de3a4
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
 2025-07-24 10:19:09 +00:00
Mallikarjun Kasoju
728681aa60 ufs: Set ufs HCLKDIV clock to 0xD0 
Set HCLKDIV to 0xD0 as per IAS.

Bug 4199271

Change-Id: I4779c74c657d8723a27a167096dfac9d22128436
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
 2025-07-24 10:19:09 +00:00
Mallikarjun Kasoju
e850611327 ufs: Enable mphy_l0_uphy_tx_fifo clock 
Enable mphy_l0_uphy_tx_fifo clock.

Bug 4199271

Change-Id: Idabbf61851446ae3f3f405ffe4fdb0a514eed01d
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
 2025-07-24 10:19:09 +00:00
Mallikarjun Kasoju
248a85dbbc ufs: Add mphy TX calibration support 
Added mphy TX calibration support.

Bug 4199271

Change-Id: Ia48945b026ac9d264d24937f9737484de8f203cd
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
 2025-07-24 10:19:09 +00:00
Laxman Dewangan
055bd73cbb camera: Use conftest for finding tegra264_io_pad_power_* available 
Use conftest for finding whether APIs tegra264_io_pad_power_*
are available or not before using it.

Bug 4911768

Change-Id: Ic8df4a0109a270d5a486a67900ed7fe4c57b79be
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
 2025-07-24 10:19:09 +00:00
Dara Ramesh
09d2e16146 tegra-virt-alt: Added support for T264 ADSP Audio 
Added new DT compatible string for t264
Extended T210 MUX/CTRL to use for T264

Bug 4635899

Change-Id: Ia2b2c8bc77eba65bf3530f28ccb1d23bcf93e0dd
 2025-07-24 10:19:09 +00:00
Dara Ramesh
ed4c071bfa tegra-virt-alt: T264 ADSP support for machine driver 
Extended T210 ADSP DAI LINKS  to use for T264

Bug 4635899

Change-Id: I613698aef930458f031462ddc7fd8bfbe72768a3
 2025-07-24 10:19:09 +00:00
Sheetal
7e6dc18387 tegra-virt-alt: Unify Mixer controls with L4T 
- Rename the mixer controls to match with L4T mixer controls.
- As most of the controls are matching between t234 and t264,
  the difference controls are added as part of component driver
  probe.
- Comment ARAD and regdump controls as ARAD and regdump are
  non-functional currently.
- Remove unused controls. MIXER, ASRC and AMX Enable controls are
  not required to be set explicitly as AudioServer handles this.

Bug 4796520

Change-Id: Ia6fdd507819b1b354544b2b1217d9aa399e106b9
Signed-off-by: Sheetal <sheetal@nvidia.com>
 2025-07-24 10:19:09 +00:00
Mikko Perttunen
e71627a4e5 drm/tegra: vic: Fix CRC enable for T264 
The change to write the INTF_CRC_CFG register was inadvertently
left out. Correct this.

Bug 4809300

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: I208da56d03e90e72ce26dffe7bef1cdeab95fab6
 2025-07-24 10:19:09 +00:00
Uday Gupta
c8cb7c0808 Updated changes for XBAR 
Change-Id: Ibb90f15b2a1edad00abbd2c5a3ab149ba9b468a6
Signed-off-by: Uday Gupta <udayg@nvidia.com>
 2025-07-24 10:19:09 +00:00
Mikko Perttunen
6cf81885cf CRC enable for Tegra264 
Change-Id: I9f38b199c36a0baf600a68e9dfd344440abe7fa0
 2025-07-24 10:19:09 +00:00
Vishwaroop A
e147027277 drivers: spi: update misc register programming 
Update the misc register programming for T264
for slave.

Bug 4711327

Change-Id: Ia6409bbee66e9984f83ad792d67c730fa637f58d
Signed-off-by: Vishwaroop A <va@nvidia.com>
 2025-07-24 10:19:09 +00:00
vasukis
7789bd9c0a tegra: hwpm: VIC: HWPM-NvHost Profiling support 
Add support to profile NvHost IPs on various chips
by HWPM module.

Bug 4170421
DOS-SHR-7966

Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: I42ac3b5fa79d7b6f97e66098cb84277cda2aff4d
 2025-07-24 10:19:09 +00:00
Vishwaroop A
32ae8fdb4c drivers: tach: add support for 1MHZ clock 
T264 has 1MHz clock for tach. Add support for this
clock.

Signed-off-by: Vishwaroop A <va@nvidia.com>
Change-Id: Ic2ecc5dd2494f3b55340f1b925ca616c4844ed6f
 2025-07-24 10:19:09 +00:00
Akihiro Mizusawa
dadd61f04c tegra rtcpu: add debug map test buffers for ISP1 
Add debug map test buffers for ISP1.

Jira CT26X-427

Change-Id: If3f12b789263aa3d8dbbb3b88157cce429335ea9
Signed-off-by: Akihiro Mizusawa <amizusawa@nvidia.com>
 2025-07-24 10:19:09 +00:00