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scsi: ufs: Set pll3 rate_b

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Set PLL3 RATEB rate as 582400000.

Bug 4757621

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I18652261b7224d162a502de3d30e5eb354fd6675
This commit is contained in:
Mallikarjun Kasoju
2024-10-08 12:52:21 +00:00
committed by Jon Hunter
parent fb95615c17
commit f66b44645e
2 changed files with 10 additions and 2 deletions
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11
drivers/scsi/ufs/ufs-tegra-common.c
View File

@@ -755,6 +755,7 @@ static int ufs_tegra_enable_ufs_uphy_pll3(struct ufs_tegra_host *ufs_tegra,
{
int err = 0;
struct device *dev = ufs_tegra->hba->dev;
unsigned long rate_b_freq;
if (!ufs_tegra->configure_uphy_pll3)
return 0;
@@ -765,9 +766,15 @@ static int ufs_tegra_enable_ufs_uphy_pll3(struct ufs_tegra_host *ufs_tegra,
return err;
if (is_rate_b) {
if (ufs_tegra->ufs_uphy_pll3)
if (ufs_tegra->ufs_uphy_pll3) {
if (ufs_tegra->soc->chip_id == TEGRA264)
rate_b_freq = UFS_CLK_UPHY_PLL3_RATEB_T264;
else
rate_b_freq = UFS_CLK_UPHY_PLL3_RATEB;
err = clk_set_rate(ufs_tegra->ufs_uphy_pll3,
UFS_CLK_UPHY_PLL3_RATEB);
rate_b_freq);
}
} else {
if (ufs_tegra->ufs_uphy_pll3)
err = clk_set_rate(ufs_tegra->ufs_uphy_pll3,

1
drivers/scsi/ufs/ufs-tegra.h
View File

@@ -163,6 +163,7 @@
/*Uphy pll clock defines*/
#define UFS_CLK_UPHY_PLL3_RATEA 4992000000
#define UFS_CLK_UPHY_PLL3_RATEB 5840000000
#define UFS_CLK_UPHY_PLL3_RATEB_T264 582400000
/* HS clock frequencies */
#define MPHY_TX_HS_BIT_DIV_CLK 600000000