Issue: MAC loopback is not getting enabled with below sequence
step1> enable MAC loopback via ioctl call
step2> bring down then bring up interface
step3> re-enable MAC loopback via ioctl call
Fix:
Reset MAC loopback variable if it is enabled, while
interface is going down. So that IOCTL path can
reconfigure the MAC loopback settings in MAC HW.
Bug 3445596
Change-Id: I01ce6551aaded409af02183e166396a7597c3b51
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2640912
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Issue:
- Workqueue for Tx timestamp is running without
delay, use many CPU cycle at hard isr thread
priority.
- Incorrect return value from ether_handle_tso()
Fix:
- Update code to use delayed workqueue
- Return correct value
Bug 200780891
Bug 3400623
Change-Id: I2095a0634e079bf870ef87cd2de1d35fe24bafd4
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2610986
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Issue:
1) usuage of SUPPORTED_* in PHY driver for setting
the link mode parameters leading data corruption. So
replaced SUPPORTED_* with linkmode_*_bit in PHY driver.
2) Redundant code of setting Pause of PHY
Fix:
1) Change SUPPORTED_* to ETHTOOL_LINK_MODE_*_BIT for
consistent check between PHY and Ethernet driver for K5.10.
2) removed pause setting of PHY, since this is already
taken care in corresponding PHY drivers.
Bug 200781153
Change-Id: Ic6a212dd4560fb3a06a4f60be3bdd33620a38197
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2607712
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Issue: mdio bus is registered in probe and before exiting
probe ethernet clocks are disabled to save power. When SC7
is initiated then PHY framework invokes a PHY suspend which
triggers the PHY register write. Since clocks are not enabled
PHY register write is ignored and returned failure which
inturn prevented the entire system to enter into SC7
Fix: Move mdio bus registration to open so that PHY reads/writes
will not be invoked before bringing up the ethernet interface.
Bug 3368603
Change-Id: Idc74be76f47ca1cb607502a4572cb2001d42903a
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2607300
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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Issue:
To save more power PHY RXC will be disabled when PHY in LPI state by
setting 10th bit in below register. This is standard PHY register.
- PCS Control 1 register (MMD device 3, Address 0x00)
When EEE enabled above register being programmed (10th bit got set) and
it created issue while accessing the MAC registers through indirect
addressing since RXC stopped from PHY.
Fix:
Don't stop RXC in LPI for Orin EQOS
Bug 200776300
Bug 200765092
Change-Id: I4150eebe8e2a5ab79ad5b7180232adad2331e315
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2599137
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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Issue:
- TX packet fragments are not working
on Orin platform.
- Express packets pass through even time
interval is not sufficient to send packet
Fix:
- Set OSI_PKT_CX_LEN and tx_pkt_cx->payload_len
for non TSO packet. this will update frame
length in TDECS3
Bug 200765943
Bug 200763256
Change-Id: I82cc91e176d9ac84d654ef7f60686ebc4024d3da
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2592048
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Issue: SID needs to be programmed through HV window
to get it reflected in controller register space.
Currently its programmed through RM window.
Fix: Get HV window base address from DT and program
in controller registers in non-hypervisor mode.
Store MAC instance ID to program the same ASID
values which are used in DT.
Bug 200761024
Change-Id: Ie9bcaebcba39f2d07438c9502591c0f51f22378f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2592481
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Issue: MGBE supports upto 16K jumbo size.
There is enough MTL queue space also
for 16K packet even with all 10 queues
enabled in MGBE. So no need to restrict
> 9k jumbo to single channel config only.
FIx: For MGBE, unconditionally allow upto 16K
jumbo size setting.
Bug 200760072
Change-Id: I734ce3be13605e4db992a1679e2de0736bd2583f
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2579108
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Issue
- Driver probe defer causes failed prints on kernel boot logs
if clk/reset controller driver module is not initialized
before nvethernet module probe.
Fix
- The probe defer is part of kernel mechanism to retry module
initialization and hardware setup. This is not an error
or failure for software driver.
Only in case of probe failure, throw error logs in console
Bug 200728771
Bug 200732811
Change-Id: I9c421db6ceedc108553f9f2b33f4f3993d63c02f
Signed-off-by: Sushil Singh <sushilkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2563340
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ifr_data pointer value used to carry mii_ioctl_data from
user space to kernel space. When all values are zero it
reflects the pointer value as zero and ifr_data NULL pointer
check will result in failure.
Driver should not check since ifr_data pointer value itself
represent mii_ioctl_data. So removing the NULL check for ifr_data.
Bug 200733774
Change-Id: Ibf405fe22c3e2e694e08eac598e9431066703c3c
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2564428
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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Algorithm:
- There is one master queue and one final queue to maintain the
packets.
- Final queue will start when a packet received with TTL=1
- TTL = 2 and 3 packets will be queued into final if those are in
sequence else those will be queued to master queue.
- When packet received with TTL = 2 then only merge process will start
- For every valid final queue merge starts by looking at the IPID
in master queue in increment order. This loop continues until
TTL = 2 found in master queue.
- Once TTL = 2 found then entire final queue will be given GRO
layer in sequential order.
Bug 3106903
Change-Id: I6cc08f3faae67a04813d32d59f7cce02f06dccbf
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2554423
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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BPMP-FW exposes the following MGBE RX clocks:
o mgbe0_rx_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_input_m [monitoring clk: virtual clk controls RX clk FMON]
o mgbe0_rx_pcs_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_pcs [mux between mgbe0_rx_pcs_input and mgbe0_tx_pcs]
o mgbe0_rx_pcs_m [monitoring clk: virtual clk controls RX PCS clk FMON]
To enable RX clock FMON -
o Issue clk_set_rate on MGBE_RX_INPUT and MGBE_RX_PCS_INPUT based
on UPHY GBE mode.
o Clk_enable already available on ToT for RX_INPUT_M
and RX_PCS_INPUT_M.
Bug 3288030
Change-Id: Ia71ccc9f21a5e79fecf149efae9032db25af60d8
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2544758
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
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GVS: Gerrit_Virtual_Submit
- On transmit complete callback
-- If OSI_TXDONE_CX_TS_DELAY flag is set in Tx done
flag, store buffer pointer along with pkt Id
in its internal array/list
- On Common interrupt:
-- Call osi to handle common interrupt.
- On trasmit complete interrupt:
-- Parse through internal array/list for pending TS
to read, by issuing OSI_CMD_GET_TS ioctl for pkt_id.
Loop until list is cleared or error is received.
-- On interface up
Remove old timestamp of channels initialized.
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Change-Id: I5104277de66dd240023f921fa5f7b4fcc035f74d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2535962
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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GVS: Gerrit_Virtual_Submit
There are three clks for MGBE which needs to be set based
on UPHY GBE mode and PHY line rate.
o MGBE_MAC_DIV_CLK will be set based on PHY line rate
o MGBE_MAC_TX/TX_PCS clks will be set based on UPHY GBE mode
Below are the settings -
UPHY GBE mode = 10G:
===================
Possible MAC working rates: 10G/5G/2.5G
1) MAC DIVISOR: 312.5MHz, 312.5/2MHZ and 312.5/4MHz
2) TX CLK: 644.5MHZ
3) TX PCS_CLK: 156.5MHz
UPHY GBE mode = 5G:
==================
Possible MAC working rates: 5G/2.5G
1) MAC DIVISOR: 312.5/2MHz and 312.5/4MHz
2) TX CLK: 322.2MHZ
3) TX PCS_CLK: 78.125MHz
Bug 200739493
Change-Id: Ie6b21f87d2077b8be621a32b2034b4eff1eb391e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2541313
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
