Algorithm:
- There is one master queue and one final queue to maintain the
packets.
- Final queue will start when a packet received with TTL=1
- TTL = 2 and 3 packets will be queued into final if those are in
sequence else those will be queued to master queue.
- When packet received with TTL = 2 then only merge process will start
- For every valid final queue merge starts by looking at the IPID
in master queue in increment order. This loop continues until
TTL = 2 found in master queue.
- Once TTL = 2 found then entire final queue will be given GRO
layer in sequential order.
Bug 3106903
Change-Id: I6cc08f3faae67a04813d32d59f7cce02f06dccbf
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2554423
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
BPMP-FW exposes the following MGBE RX clocks:
o mgbe0_rx_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_input_m [monitoring clk: virtual clk controls RX clk FMON]
o mgbe0_rx_pcs_input [external input clk recovered from GBE UPHY lane]
o mgbe0_rx_pcs [mux between mgbe0_rx_pcs_input and mgbe0_tx_pcs]
o mgbe0_rx_pcs_m [monitoring clk: virtual clk controls RX PCS clk FMON]
To enable RX clock FMON -
o Issue clk_set_rate on MGBE_RX_INPUT and MGBE_RX_PCS_INPUT based
on UPHY GBE mode.
o Clk_enable already available on ToT for RX_INPUT_M
and RX_PCS_INPUT_M.
Bug 3288030
Change-Id: Ia71ccc9f21a5e79fecf149efae9032db25af60d8
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2544758
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
- On transmit complete callback
-- If OSI_TXDONE_CX_TS_DELAY flag is set in Tx done
flag, store buffer pointer along with pkt Id
in its internal array/list
- On Common interrupt:
-- Call osi to handle common interrupt.
- On trasmit complete interrupt:
-- Parse through internal array/list for pending TS
to read, by issuing OSI_CMD_GET_TS ioctl for pkt_id.
Loop until list is cleared or error is received.
-- On interface up
Remove old timestamp of channels initialized.
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Change-Id: I5104277de66dd240023f921fa5f7b4fcc035f74d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2535962
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
There are three clks for MGBE which needs to be set based
on UPHY GBE mode and PHY line rate.
o MGBE_MAC_DIV_CLK will be set based on PHY line rate
o MGBE_MAC_TX/TX_PCS clks will be set based on UPHY GBE mode
Below are the settings -
UPHY GBE mode = 10G:
===================
Possible MAC working rates: 10G/5G/2.5G
1) MAC DIVISOR: 312.5MHz, 312.5/2MHZ and 312.5/4MHz
2) TX CLK: 644.5MHZ
3) TX PCS_CLK: 156.5MHz
UPHY GBE mode = 5G:
==================
Possible MAC working rates: 5G/2.5G
1) MAC DIVISOR: 312.5/2MHz and 312.5/4MHz
2) TX CLK: 322.2MHZ
3) TX PCS_CLK: 78.125MHz
Bug 200739493
Change-Id: Ie6b21f87d2077b8be621a32b2034b4eff1eb391e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2541313
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Linux OSD code maintaining link list to identify L2
filter added/removed in compare to earlier list.
By doing this OSD sends address and dma channel which
should to be removed from hardware instead of full
list every time.
Bug 200711542
Bug 200711544
Bug 200713215
Change-Id: I95d4dc687c5fd45a6e0bbc3c097e59b90b03b0e5
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2519592
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Issue:
1) Missing support for packet MC/BC packet duplication
2) Remove MAC UC and BC address on ether_close()
Fix:
1) Update OSI_CMD_L2_FILTER structure parameter to support
new algorithm.
2) MAC UC and BC address added to filter from ether_open()
and ether_resume() function.
3) Configure MAC register to support MC/BC packet
duplication
Bug 200711542
Bug 200711544
Bug 200713215
Change-Id: Ie589892de121e5873f5dfa9b9db9bf5c441ece71
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2519591
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
This commit adds the driver interface for the
MACsec controller. The driver interface is
invoked using generic netlink messages from
userspace MACsec key agreement agent.
Currently sysfs node is added to check the irq
stats for default macsec controller operation.
Bug 2913560
Change-Id: I07b0b778ba1c6674e87b103a3e68e158fea61c2c
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
- Add a new DT node to enable Multiple DMA routing
for netdev MC MAC ddress. Read the DT value
and store it into OSI core private data.
- Add new driver private IOCTL for MC DMA channels
selection as inputs and call ether_set_rx_mode
to update MAC filters with given DMA channels route.
Bug 200565911
Change-Id: I1e65322489e34c4b6318a769dac963073d4887ad
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Issue: DMA will be in suspend state if there is no rx buffer allocation
happen to HW. If DMA is in suspend state, no interrupt will
occur for channel which leads to not calling of
osd_receive_packet().
Fix: Whenever there is rx buffer kernel memory allocation failure,
desc will be updated with reserve buffer. This reserved RX buffer
is already allocated at the time of eqos_open. Aim of same to
make sure rx DMA always have buffer and not go in suspend state.
Bug 200650229
Change-Id: Ic18d9f8f03c69c142d91288a1a7288d26e1c8b42
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2399011
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Fix build linux-5.7-rc5 errors including following:
- change timespec to timespec64. replace getnstimeofday
with ktime_get_ts64
- replace usage of macro FIELD_SIZEOF with sizeof_field in ethtool.c
nvethernet and eqos files.
- support 2 arguments for of_get_phy_mode call
bug 200617764
Change-Id: I46067d7d36d08ee9556b2722e9ccec707b8853d4
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2347244
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Adds VM interrupt handling for VM interrupt
based MAC controllers.
Need to pass below parameters from DT -
o Number of VM IRQ's assigned per OS/VM.
o Number of VM channels assigned to a VM IRQ.
o List of DMA channels assigned to a VM IRQ.
Below is the sample DT representation -
vm_irq_config: vm-irq-config {
nvidia,num-vm-irqs = <4>;
vm_irq1 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <0 1>;
};
vm_irq2 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <2 3>;
};
vm_irq3 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <4 5>;
};
vm_irq4 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <6 7>;
};
};
ethernet@<base_addr> {
[...]
nvidia,vm-irq-config = <&vm_irq_config>;
[...]
}
Bug 200548572
Change-Id: I802f247fa95ef6dcd769afbc7c13c6362d2f328e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2292602
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
1. Add Flag which decides stats work queue is enabled(1) or
disabled(0)
2. If virtualization is enabled then allow function driver instance
to specify non zero DMA channel and to read stats flag from DT.
Bug 2694285
Change-Id: Ic97c079e66c117ed78f1b473ffda33173bd3f23c
Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Change-Id: Ic97c079e66c117ed78f1b473ffda33173bd3f23c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2327179
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tx frame count and software timer based interrupt coalescing
is enabled. Tx frame count based interrupt coalescing can be
enabled only when tx software timer based interrupt coalescing
is also enabled.
Bug 200529168
Change-Id: I8ac701c86238e8d34d7dbe9924df1162083c023e
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2234610
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
