prafulls 02a15c114a video: tegra: bridge: Enable CRC check for MAX Ser
This change enables internal video CRC check for
Maxim DP Serializer.

1. This sets the bit to enable CRC functionality
   and then add handlers for ERRB CRC errors.
2. Reading register clears the error.
3. Error can be injected using i2c tool to write
   error inject bit in register.

Below is flow to verify CRC functionality
1. Run GFX application like bubble
2. Read VTX41 register and confirm VID_ASIL_CRC_ERR bit is not set
3. Inject error by setting bit VID_ASIL_INJ_ERR.
4. Verify dmesg errors.

bug 3463178

Change-Id: I25c07413eb81bb4b40f35e15b53a4102ec68fa9e
Signed-off-by: prafulls <prafulls@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2751057
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Shu Zhong <shuz@nvidia.com>
GVS: Gerrit_Virtual_Submit
2023-04-11 04:35:05 +00:00
2022-09-10 23:43:40 -07:00
2022-12-07 23:57:14 -08:00
2023-04-07 00:12:26 -07:00
Description
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34 MiB