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01ecacf7b4
- smmu and hsp support added for fsicom multi core feature in fsicom kernel driver - probe, suspend and resume will be called for smmu_inst 0 only as it will have single dev node for comm. - mailbox 2,5 and 1,4 is used for TX and RX comm. respectively with FSI Jira SS-5744 Change-Id: I859d5945853195ba76996a8c36ca19efd9c4409f Signed-off-by: pshaw <pshaw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2952268 Reviewed-by: Praveen James <pjames@nvidia.com> Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
43 lines
982 B
C
43 lines
982 B
C
/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note)
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*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION, All rights reserved.
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*/
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#ifndef _UAPI_TEGRA_FSICOM_H_
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#define _UAPI_TEGRA_FSICOM_H_
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#include <linux/ioctl.h>
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#define MAX_FSI_CORE 2
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struct rw_data {
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uint8_t coreid;
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uint32_t handle;
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uint64_t pa;
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uint64_t iova;
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uint64_t dmabuf;
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uint64_t attach;
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uint64_t sgt;
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};
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/*Data type for sending the offset,IOVA and channel Id details to FSI */
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struct iova_data {
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uint8_t coreid;
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uint32_t offset;
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uint32_t iova;
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uint32_t chid;
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};
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/* signal value */
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#define SIG_DRIVER_RESUME 43
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#define SIG_FSI_WRITE_EVENT 44
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/* ioctl call macros */
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#define NVMAP_SMMU_MAP _IOWR('q', 1, struct rw_data *)
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#define NVMAP_SMMU_UNMAP _IOWR('q', 2, struct rw_data *)
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#define TEGRA_HSP_WRITE _IOWR('q', 3, struct rw_data *)
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#define TEGRA_SIGNAL_REG _IOWR('q', 4, struct rw_data *)
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#define TEGRA_IOVA_DATA _IOWR('q', 5, struct iova_data *)
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#endif /* _UAPI_TEGRA_FSICOM_H_ */
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