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25074f2a0c
Add mc-utils OOT module which is used by clients to get information regarding MC and EMC parameters. Bug 3826001 Change-Id: Ic03405bd1f6f6ba4bb11082c0e94c67e99cfbb6d Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2805684 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
351 lines
7.8 KiB
C
351 lines
7.8 KiB
C
/**
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/export.h>
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#include <linux/types.h>
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#include <linux/debugfs.h>
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#include <linux/clk.h>
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#include <linux/platform/tegra/mc_utils.h>
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#include <linux/version.h>
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#include <soc/tegra/fuse.h>
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#include <linux/io.h>
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#define BYTES_PER_CLK_PER_CH 4
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#define CH_16 16
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#define CH_8 8
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#define CH_4 4
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#define CH_16_BYTES_PER_CLK (BYTES_PER_CLK_PER_CH * CH_16)
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#define CH_8_BYTES_PER_CLK (BYTES_PER_CLK_PER_CH * CH_8)
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#define CH_4_BYTES_PER_CLK (BYTES_PER_CLK_PER_CH * CH_4)
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/* EMC regs */
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#define MC_BASE 0x02c10000
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#define EMC_BASE 0x02c60000
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#define MCB_BASE 0x02c10000
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#define MCB_SIZE 0x10000
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#define EMC_FBIO_CFG5_0 0x100C
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#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0 0xdf8
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#define MC_EMEM_ADR_CFG_0 0x54
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#define MC_ECC_CONTROL_0 0x1880
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#define CH_MASK 0xFFFF /* Change bit counting if this mask changes */
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#define CH4 0xf
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#define CH2 0x3
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#define ECC_MASK 0x1 /* 1 = enabled, 0 = disabled */
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#define RANK_MASK 0x1 /* 1 = 2-RANK, 0 = 1-RANK */
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#define DRAM_MASK 0x3
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/* EMC_FBIO_CFG5_0(1:0) : DRAM_TYPE */
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#define DRAM_LPDDR4 0
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#define DRAM_LPDDR5 1
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#define DRAM_DDR3 2
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#define BR4_MODE 4
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#define BR8_MODE 8
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/* BANDWIDTH LATENCY COMPONENTS */
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#define SMMU_DISRUPTION_DRAM_CLK_LP4 6003
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#define SMMU_DISRUPTION_DRAM_CLK_LP5 9005
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#define RING0_DISRUPTION_MC_CLK_LP4 63
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#define RING0_DISRUPTION_MC_CLK_LP5 63
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#define HUM_DISRUPTION_DRAM_CLK_LP4 1247
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#define HUM_DISRUPTION_DRAM_CLK_LP5 4768
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#define HUM_DISRUPTION_NS_LP4 1406
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#define HUM_DISRUPTION_NS_LP5 1707
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#define EXPIRED_ISO_DRAM_CLK_LP4 424
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#define EXPIRED_ISO_DRAM_CLK_LP5 792
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#define EXPIRED_ISO_NS_LP4 279
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#define EXPIRED_ISO_NS_LP5 279
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#define REFRESH_RATE_LP4 176
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#define REFRESH_RATE_LP5 226
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#define PERIODIC_TRAINING_LP4 380
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#define PERIODIC_TRAINING_LP5 380
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#define CALIBRATION_LP4 30
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#define CALIBRATION_LP5 30
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struct emc_params {
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u32 rank;
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u32 ecc;
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u32 ch;
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u32 dram;
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};
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static struct emc_params emc_param;
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static u32 ch_num;
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static enum dram_types dram_type;
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static unsigned long freq_to_bw(unsigned long freq)
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{
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if (ch_num == CH_16)
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return freq * CH_16_BYTES_PER_CLK;
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if (ch_num == CH_8)
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return freq * CH_8_BYTES_PER_CLK;
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/*4CH and 4CH_ECC*/
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return freq * CH_4_BYTES_PER_CLK;
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}
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static unsigned long bw_to_freq(unsigned long bw)
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{
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if (ch_num == CH_16)
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return (bw + CH_16_BYTES_PER_CLK - 1) / CH_16_BYTES_PER_CLK;
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if (ch_num == CH_8)
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return (bw + CH_8_BYTES_PER_CLK - 1) / CH_8_BYTES_PER_CLK;
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/*4CH and 4CH_ECC*/
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return (bw + CH_4_BYTES_PER_CLK - 1) / CH_4_BYTES_PER_CLK;
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}
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unsigned long emc_freq_to_bw(unsigned long freq)
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{
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return freq_to_bw(freq);
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}
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EXPORT_SYMBOL(emc_freq_to_bw);
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unsigned long emc_bw_to_freq(unsigned long bw)
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{
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return bw_to_freq(bw);
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}
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EXPORT_SYMBOL(emc_bw_to_freq);
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u8 get_dram_num_channels(void)
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{
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return ch_num;
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}
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EXPORT_SYMBOL(get_dram_num_channels);
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/* DRAM clock in MHz
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*
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* Return: MC clock in MHz
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*/
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unsigned long dram_clk_to_mc_clk(unsigned long dram_clk)
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{
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unsigned long mc_clk;
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if (dram_clk <= 1600)
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mc_clk = (dram_clk + BR4_MODE - 1) / BR4_MODE;
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else
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mc_clk = (dram_clk + BR8_MODE - 1) / BR8_MODE;
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return mc_clk;
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}
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EXPORT_SYMBOL(dram_clk_to_mc_clk);
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static void set_dram_type(void)
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{
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dram_type = DRAM_TYPE_INVAL;
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switch (emc_param.dram) {
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case DRAM_LPDDR5:
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if (emc_param.ecc) {
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if (ch_num == 16) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_16CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_16CH_ECC_1RANK;
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} else if (ch_num == 8) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_8CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_8CH_ECC_1RANK;
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} else if (ch_num == 4) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_ECC_1RANK;
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}
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} else {
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if (ch_num == 16) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_16CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_16CH_1RANK;
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} else if (ch_num == 8) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_8CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_8CH_1RANK;
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} else if (ch_num == 4) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_1RANK;
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}
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}
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if (ch_num < 4) {
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pr_err("DRAM_LPDDR5: Unknown memory channel configuration\n");
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WARN_ON(true);
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}
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break;
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case DRAM_LPDDR4:
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if (emc_param.ecc) {
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if (ch_num == 16) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_16CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_16CH_ECC_1RANK;
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} else if (ch_num == 8) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_8CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_8CH_ECC_1RANK;
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} else if (ch_num == 4) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_4CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_4CH_ECC_1RANK;
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}
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} else {
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if (ch_num == 16) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_16CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_16CH_1RANK;
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} else if (ch_num == 8) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_8CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_8CH_1RANK;
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} else if (ch_num == 4) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_1RANK;
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}
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}
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if (ch_num < 4) {
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pr_err("DRAM_LPDDR4: Unknown memory channel configuration\n");
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WARN_ON(true);
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}
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break;
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default:
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pr_err("mc_util: ddr config not supported\n");
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WARN_ON(true);
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}
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}
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enum dram_types tegra_dram_types(void)
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{
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return dram_type;
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}
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EXPORT_SYMBOL(tegra_dram_types);
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#if defined(CONFIG_DEBUG_FS)
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static void tegra_mc_utils_debugfs_init(void)
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{
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struct dentry *tegra_mc_debug_root = NULL;
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tegra_mc_debug_root = debugfs_create_dir("tegra_mc_utils", NULL);
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if (IS_ERR_OR_NULL(tegra_mc_debug_root)) {
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pr_err("tegra_mc: Unable to create debugfs dir\n");
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return;
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}
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debugfs_create_u32("dram_type", 0444, tegra_mc_debug_root,
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&dram_type);
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debugfs_create_u32("num_channel", 0444, tegra_mc_debug_root,
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&ch_num);
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}
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#endif
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static int __init tegra_mc_utils_init(void)
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{
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u32 dram, ch, ecc, rank;
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void __iomem *emc_base;
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void __iomem *mcb_base;
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emc_base = ioremap(EMC_BASE, 0x00010000);
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dram = readl(emc_base + EMC_FBIO_CFG5_0) & DRAM_MASK;
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mcb_base = ioremap(MCB_BASE, MCB_SIZE);
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if (!mcb_base) {
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pr_err("Failed to ioremap\n");
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return -ENOMEM;
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}
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ch = readl(mcb_base + MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0);
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ch &= CH_MASK;
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/*
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* TODO: For non orin chips MC_ECC_CONTROL_0 is not present, hence set
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* ecc to 0 and cleanup this once we have chip specific mc_utils driver.
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*/
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ecc = readl(mcb_base + MC_ECC_CONTROL_0) & ECC_MASK;
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rank = readl(mcb_base + MC_EMEM_ADR_CFG_0) & RANK_MASK;
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iounmap(emc_base);
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iounmap(mcb_base);
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while (ch) {
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if (ch & 1)
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ch_num++;
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ch >>= 1;
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}
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emc_param.ch = ch;
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emc_param.ecc = ecc;
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emc_param.rank = rank;
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emc_param.dram = dram;
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set_dram_type();
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#if defined(CONFIG_DEBUG_FS)
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tegra_mc_utils_debugfs_init();
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#endif
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return 0;
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}
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module_init(tegra_mc_utils_init);
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static void __exit tegra_mc_utils_exit(void)
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{
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}
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module_exit(tegra_mc_utils_exit);
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MODULE_DESCRIPTION("MC utility provider module");
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MODULE_AUTHOR("Puneet Saxena <puneets@nvidia.com>");
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MODULE_AUTHOR("Ashish Mhetre <amhetre@nvidia.com>");
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MODULE_LICENSE("GPL v2");
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