mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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ad95189d09
Add clock, reset and stream-id header files and include them in the overlay dts. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Change-Id: I1835cff21c34b143e58ead405af7f64bd9a6cb89 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2763002 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
143 lines
5.1 KiB
C
143 lines
5.1 KiB
C
/*
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* Copyright (c) 2018-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* NVIDIA CORPORATION and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA CORPORATION is strictly prohibited.
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*/
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#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_OOT_H
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#define DT_BINDINGS_RESET_TEGRA234_RESET_OOT_H
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/**
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* @file
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* @defgroup bpmp_reset_ids Reset ID's
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* @brief Identifiers for Resets controllable by firmware
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* @{
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*/
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#define TEGRA234_RESET_ACTMON 1U
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#define TEGRA234_RESET_ADSP_ALL 2U
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#define TEGRA234_RESET_DSI_CORE 3U
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#define TEGRA234_RESET_CAN1 4U
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#define TEGRA234_RESET_CAN2 5U
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#define TEGRA234_RESET_DLA0 6U
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#define TEGRA234_RESET_DLA1 7U
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#define TEGRA234_RESET_DPAUX 8U
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#define TEGRA234_RESET_OFA 9U
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#define TEGRA234_RESET_NVJPG1 10U
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#define TEGRA234_RESET_NVDISPLAY 16U
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#define TEGRA234_RESET_EQOS 17U
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#define TEGRA234_RESET_GPCDMA 18U
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#define TEGRA234_RESET_GPU 19U
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#define TEGRA234_RESET_EQOS_MACSEC 22U
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#define TEGRA234_RESET_EQOS_MACSEC_SECURE 23U
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#define TEGRA234_RESET_ISP 36U
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#define TEGRA234_RESET_MIPI_CAL 37U
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#define TEGRA234_RESET_MPHY_CLK_CTL 38U
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#define TEGRA234_RESET_MPHY_L0_RX 39U
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#define TEGRA234_RESET_MPHY_L0_TX 40U
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#define TEGRA234_RESET_MPHY_L1_RX 41U
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#define TEGRA234_RESET_MPHY_L1_TX 42U
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#define TEGRA234_RESET_NVCSI 43U
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#define TEGRA234_RESET_NVDEC 44U
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#define TEGRA234_RESET_MGBE0_MACSEC 47U
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#define TEGRA234_RESET_MGBE0_MACSEC_SECURE 48U
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#define TEGRA234_RESET_MGBE1_MACSEC 51U
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#define TEGRA234_RESET_MGBE1_MACSEC_SECURE 52U
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#define TEGRA234_RESET_MGBE2_MACSEC 55U
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#define TEGRA234_RESET_NVENC 59U
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#define TEGRA234_RESET_MGBE2_MACSEC_SECURE 60U
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#define TEGRA234_RESET_NVJPG 61U
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/* RESERVED 62:63 */
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#define TEGRA234_RESET_LA 64U
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#define TEGRA234_RESET_HWPM 65U
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#define TEGRA234_RESET_PVA0_ALL 66U
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#define TEGRA234_RESET_CEC 67U
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#define TEGRA234_RESET_I2S7 78U
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#define TEGRA234_RESET_I2S8 79U
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#define TEGRA234_RESET_SCE_ALL 80U
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#define TEGRA234_RESET_RCE_ALL 81U
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#define TEGRA234_RESET_SDMMC1 82U
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#define TEGRA234_RESET_RSVD_83 83U
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#define TEGRA234_RESET_RSVD_84 84U
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/* RESERVED 86 */
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#define TEGRA234_RESET_MGBE3_MACSEC 89U
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#define TEGRA234_RESET_MGBE3_MACSEC_SECURE 90U
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#define TEGRA234_RESET_SPI1 91U
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#define TEGRA234_RESET_SPI2 92U
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#define TEGRA234_RESET_SPI3 93U
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#define TEGRA234_RESET_SPI4 94U
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#define TEGRA234_RESET_TACH0 95U
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#define TEGRA234_RESET_TACH1 96U
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#define TEGRA234_RESET_SPI5 97U
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#define TEGRA234_RESET_TSEC 98U
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#define TEGRA234_RESET_UARTI 99U
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#define TEGRA234_RESET_UARTB 101U
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#define TEGRA234_RESET_UARTC 102U
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#define TEGRA234_RESET_UARTD 103U
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#define TEGRA234_RESET_UARTE 104U
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#define TEGRA234_RESET_UARTF 105U
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#define TEGRA234_RESET_UARTJ 106U
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#define TEGRA234_RESET_UARTH 107U
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#define TEGRA234_RESET_UFSHC 108U
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#define TEGRA234_RESET_UFSHC_AXI_M 109U
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#define TEGRA234_RESET_UFSHC_LP_SEQ 110U
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#define TEGRA234_RESET_RSVD_111 111U
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#define TEGRA234_RESET_VI 112U
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#define TEGRA234_RESET_XUSB_PADCTL 114U
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#define TEGRA234_RESET_VI2 115U
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#define TEGRA234_RESET_RSVD_127 127U
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#define TEGRA234_RESET_NVHS_UPHY_PLL1 128U
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#define TEGRA234_RESET_GBE_UPHY 131U
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#define TEGRA234_RESET_GBE_UPHY_PM 132U
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#define TEGRA234_RESET_NVHS_UPHY 133U
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#define TEGRA234_RESET_NVHS_UPHY_PLL0 134U
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#define TEGRA234_RESET_NVHS_UPHY_L0 135U
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#define TEGRA234_RESET_NVHS_UPHY_L1 136U
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#define TEGRA234_RESET_NVHS_UPHY_L2 137U
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#define TEGRA234_RESET_NVHS_UPHY_L3 138U
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#define TEGRA234_RESET_NVHS_UPHY_L4 139U
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#define TEGRA234_RESET_NVHS_UPHY_L5 140U
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#define TEGRA234_RESET_NVHS_UPHY_L6 141U
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#define TEGRA234_RESET_NVHS_UPHY_L7 142U
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#define TEGRA234_RESET_NVHS_UPHY_PM 143U
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#define TEGRA234_RESET_DMIC5 144U
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#define TEGRA234_RESET_APE 145U
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#define TEGRA234_RESET_PEX_USB_UPHY 146U
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#define TEGRA234_RESET_PEX_USB_UPHY_L0 147U
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#define TEGRA234_RESET_PEX_USB_UPHY_L1 148U
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#define TEGRA234_RESET_PEX_USB_UPHY_L2 149U
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#define TEGRA234_RESET_PEX_USB_UPHY_L3 150U
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#define TEGRA234_RESET_PEX_USB_UPHY_L4 151U
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#define TEGRA234_RESET_PEX_USB_UPHY_L5 152U
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#define TEGRA234_RESET_PEX_USB_UPHY_L6 153U
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#define TEGRA234_RESET_PEX_USB_UPHY_L7 154U
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#define TEGRA234_RESET_PEX_USB_UPHY_PLL0 159U
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#define TEGRA234_RESET_PEX_USB_UPHY_PLL1 160U
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#define TEGRA234_RESET_PEX_USB_UPHY_PLL2 161U
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#define TEGRA234_RESET_PEX_USB_UPHY_PLL3 162U
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#define TEGRA234_RESET_GBE_UPHY_L0 163U
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#define TEGRA234_RESET_GBE_UPHY_L1 164U
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#define TEGRA234_RESET_GBE_UPHY_L2 165U
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#define TEGRA234_RESET_GBE_UPHY_L3 166U
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#define TEGRA234_RESET_GBE_UPHY_L4 167U
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#define TEGRA234_RESET_GBE_UPHY_L5 168U
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#define TEGRA234_RESET_GBE_UPHY_L6 169U
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#define TEGRA234_RESET_GBE_UPHY_L7 170U
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#define TEGRA234_RESET_GBE_UPHY_PLL0 171U
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#define TEGRA234_RESET_GBE_UPHY_PLL1 172U
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#define TEGRA234_RESET_GBE_UPHY_PLL2 173U
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#define TEGRA234_MAX_PUBLIC_RESET_ID 173U
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/** @} */
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/* FIXME: remove these dummies */
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#define TEGRA234_RESET_PCIE 0U
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#define TEGRA234_RESET_PCIEXCLK 0U
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#define TEGRA234_RESET_SE 0U
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#endif
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