Robert Huang 38578736f2 tegra-cec: Fix cec_irq flooding issue
The RX_REGISTER_FULL interrupt is not cleared when rx_fifo_data is 0.
Add readw for RX_REGISTER when rx_fifo_data is 0 so that the interrupt
can be cleared.

Bug 5266075

Change-Id: I10ab107efadc22a6ec79255e22bf080384b4ff5c
Signed-off-by: Robert Huang <robhuang@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3367190
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prafull Suryawanshi <prafulls@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2025-07-24 10:20:35 +00:00
2025-07-24 10:20:35 +00:00
2025-07-24 10:20:35 +00:00
2022-12-07 23:57:14 -08:00
2025-07-24 10:19:10 +00:00
2024-02-24 05:24:07 -08:00
Description
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34 MiB