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Issue: To save more power PHY RXC will be disabled when PHY in LPI state by setting 10th bit in below register. This is standard PHY register. - PCS Control 1 register (MMD device 3, Address 0x00) When EEE enabled above register being programmed (10th bit got set) and it created issue while accessing the MAC registers through indirect addressing since RXC stopped from PHY. Fix: Don't stop RXC in LPI for Orin EQOS Bug 200776300 Bug 200765092 Change-Id: I4150eebe8e2a5ab79ad5b7180232adad2331e315 Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2599137 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Narayan Reddy <narayanr@nvidia.com> Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>