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- when there are multiple async events back to back from DCE with very short time gap between 2 events(for example, in case of DP MST, 2 heads could be sending flip event notification back to back at almost same time), there is a possibility of 2nd async event getting processed very late when shared mailbox register is set to zero as part of processing 1st async event and before processing of 2nd async event. - current change fixes it by processing all pending IVC frames for IPC channel when processing an async event. - change few error logs to info logs as these are not actually errors. Bug 3582863 Bug 3429668 Change-Id: I29b1813bed50c4583e37f02bf656802081ccf9d3 Signed-off-by: Santosh Reddy Galma <galmar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2698560 (cherry picked from commit dd1abfa6eaab6e4f599d8c97bdccc7cbb67e1341) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2700438 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Arun Swain <arswain@nvidia.com> GVS: Gerrit_Virtual_Submit