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6f6b01c660
Currently in downstream,
* we pass FSYNC width from DT for LRCK and FSYNC modes. We also have a
mixer control to override the width. If the property is missing a
default width of "31" is set.
* DT property, "enable-cya", is used on Tegra210 to enable pad controls
for I2S4. This is not required for other instances of I2S on Tegra210
and not required for any instance on Tegra186/Tegra194.
With current patch,
* DT property "fsync-width" is removed
- LRCK mode does not require FSYNC width to be configured.
- Reset value (one-bit-clock wide) is what we are using for DSP modes.
- If specific width needs to be configured, mixer control is already
available. Generally for FSYNC modes, the width depends on the codec
and in such cases mixer control is helpful.
* DT property "enable-cya" is removed
- By default the corresponding bit is enabled.
- For other instances of I2S on Tegra210 and for any instance on
Tegra186/Tegra194, this bit is unused.
* updated the channel that needs to be used for CIF and I2S control.
For example, for CIF configuration audio channels is used and
for BCLK rate or channel bit count calculation, client channel is
used.
* helper function tegra210_i2s_set_timing_params() is added to program
I2S clock and timing related registers.
* I2S global enable is moved to default list. The enable status on TX/RX
channel is controlled via DAPM widget.
Bug 200503387
Change-Id: Iafe62e8816f6d8702a325c8466d6b6fda5514d66
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2244478
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>