mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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ADSP host driver is enhanced to be multi-instance
capable and reentrant:
- Trailing unique identifier string in compatible DT property, like
"adsp", "adsp1" or "aon", is used to identify the driver instances
- Each probed driver instance is inserted into a global list, from
which the handle can be fetched using 'nvadsp_get_handle' API
(passing the above unique identifier as argument)
- Above unique identifier is also used as name for the DBFS
directory (containing files like adsp_console, adsp_logger, etc.)
- 'nvadsp_get_handle' is the only exported API; all other APIs are
accessible via function pointers within 'struct nvadsp_handle'
- APIs above maintain one-is-to-one correspondence with all
legacy APIs, with the addition of a new argument
'struct nvadsp_handle *' at the beginning
- Legacy APIs continue to be supported, but they are hardwired to
work only if the kernel probes just one driver instance
- All driver files are cleaned up to not use any global state
variables (necessary for reentrancy)
Bug 3682950
Change-Id: Id5db49e861b2f81716ae8352b36b406654da2bbd
Signed-off-by: Viswanath L <viswanathl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3092701
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
182 lines
4.2 KiB
C
182 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include <linux/tegra_nvadsp.h>
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#include <linux/interrupt.h>
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#include <linux/version.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/virt/hv-ivc.h>
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#include "dev.h"
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#include "amc.h"
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static inline u32 amc_readl(struct nvadsp_drv_data *drv, u32 reg)
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{
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return readl(drv->base_regs[AMC] + reg);
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}
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static inline void amc_writel(struct nvadsp_drv_data *drv, u32 val, u32 reg)
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{
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writel(val, drv->base_regs[AMC] + reg);
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}
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#ifdef CONFIG_AMC_SAVE_RESTORE
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static void wmemcpy_to_aram(u32 to_aram, const u32 *from_mem, size_t wlen)
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{
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u32 base, offset;
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base = to_aram & AMC_ARAM_APERTURE_DATA_LEN;
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amc_writel(base, AMC_ARAM_APERTURE_BASE);
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offset = to_aram % AMC_ARAM_APERTURE_DATA_LEN;
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while (wlen--) {
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if (offset == AMC_ARAM_APERTURE_DATA_LEN) {
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base += AMC_ARAM_APERTURE_DATA_LEN;
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amc_writel(base, AMC_ARAM_APERTURE_BASE);
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offset = 0;
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}
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amc_writel(*from_mem, AMC_ARAM_APERTURE_DATA_START + offset);
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from_mem++;
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offset += 4;
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}
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}
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static void wmemcpy_from_aram(u32 *to_mem, const u32 from_aram, size_t wlen)
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{
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u32 base, offset;
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base = from_aram & AMC_ARAM_APERTURE_DATA_LEN;
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amc_writel(base, AMC_ARAM_APERTURE_BASE);
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offset = from_aram % AMC_ARAM_APERTURE_DATA_LEN;
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while (wlen--) {
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if (offset == AMC_ARAM_APERTURE_DATA_LEN) {
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base += AMC_ARAM_APERTURE_DATA_LEN;
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amc_writel(base, AMC_ARAM_APERTURE_BASE);
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offset = 0;
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}
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*to_mem = amc_readl(AMC_ARAM_APERTURE_DATA_START + offset);
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to_mem++;
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offset += 4;
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}
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}
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int nvadsp_aram_save(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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wmemcpy_from_aram(d->state.aram, AMC_ARAM_START, AMC_ARAM_WSIZE);
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return 0;
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}
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int nvadsp_aram_restore(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *ndd = platform_get_drvdata(pdev);
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wmemcpy_to_aram(AMC_ARAM_START, ndd->state.aram, AMC_ARAM_WSIZE);
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return 0;
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}
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int nvadsp_amc_save(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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u32 val, offset = 0;
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int i = 0;
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offset = 0x0;
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val = readl(d->base_regs[AMC] + offset);
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d->state.amc_regs[i++] = val;
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offset = 0x8;
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val = readl(d->base_regs[AMC] + offset);
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d->state.amc_regs[i++] = val;
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return 0;
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}
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int nvadsp_amc_restore(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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u32 val, offset = 0;
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int i = 0;
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offset = 0x0;
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val = d->state.amc_regs[i++];
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writel(val, d->base_regs[AMC] + offset);
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offset = 0x8;
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val = d->state.amc_regs[i++];
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writel(val, d->base_regs[AMC] + offset);
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return 0;
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}
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#endif /* CONFIG_AMC_SAVE_RESTORE */
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static irqreturn_t nvadsp_amc_error_int_handler(int irq, void *devid)
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{
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struct platform_device *pdev = devid;
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struct nvadsp_drv_data *drv = platform_get_drvdata(pdev);
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u32 val, addr, status, intr = 0;
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status = amc_readl(drv, AMC_INT_STATUS);
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addr = amc_readl(drv, AMC_ERROR_ADDR);
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if (status & AMC_INT_STATUS_ARAM) {
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/*
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* Ignore addresses lesser than AMC_ERROR_ADDR_IGNORE (4k)
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* as those are spurious ones due a hardware issue.
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*/
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if (!(drv->chip_data->amc_err_war) ||
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(addr > AMC_ERROR_ADDR_IGNORE))
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pr_info("nvadsp: invalid ARAM access. address: 0x%x\n",
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addr);
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intr |= AMC_INT_INVALID_ARAM_ACCESS;
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}
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if (status & AMC_INT_STATUS_REG) {
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pr_info("nvadsp: invalid AMC reg access. address: 0x%x\n",
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addr);
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intr |= AMC_INT_INVALID_REG_ACCESS;
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}
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val = amc_readl(drv, AMC_INT_CLR);
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val |= intr;
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amc_writel(drv, val, AMC_INT_CLR);
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return IRQ_HANDLED;
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}
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void nvadsp_free_amc_interrupts(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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if (drv->chip_data->amc_not_avlbl)
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return;
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if (!is_tegra_hypervisor_mode())
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devm_free_irq(dev, drv->agic_irqs[AMC_ERR_VIRQ], pdev);
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}
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int nvadsp_setup_amc_interrupts(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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int ret = 0;
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if (drv->chip_data->amc_not_avlbl)
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return ret;
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if (!is_tegra_hypervisor_mode())
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ret = devm_request_irq(dev, drv->agic_irqs[AMC_ERR_VIRQ],
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nvadsp_amc_error_int_handler, 0,
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"AMC error int", pdev);
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return ret;
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}
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