mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 17:25:35 +03:00
8f8c3d0aa9
Set default register values for AHUB modules in regmap. This will ensure after runtime suspend/resume AHUB register POR values does not get reset to 0. Bug 200039212 Change-Id: I38e4c04721450b7511404c0db2911b314b68a880 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/603339
555 lines
15 KiB
C
555 lines
15 KiB
C
/*
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* tegra210_mvc_alt.c - Tegra210 MVC driver
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*
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* Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/of_device.h>
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#include "tegra210_xbar_alt.h"
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#include "tegra210_mvc_alt.h"
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#define DRV_NAME "tegra210-mvc"
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static const struct reg_default tegra210_mvc_reg_defaults[] = {
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{ TEGRA210_MVC_AXBAR_RX_INT_MASK, 0x00000001},
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{ TEGRA210_MVC_AXBAR_RX_CIF_CTRL, 0x00007700},
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{ TEGRA210_MVC_AXBAR_TX_INT_MASK, 0x00000001},
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{ TEGRA210_MVC_AXBAR_TX_CIF_CTRL, 0x00007700},
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{ TEGRA210_MVC_CG, 0x1},
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{ TEGRA210_MVC_CTRL, 0x40000001},
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{ TEGRA210_MVC_INIT_VOL, 0x00800000},
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{ TEGRA210_MVC_TARGET_VOL, 0x00800000},
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{ TEGRA210_MVC_DURATION, 0x000012c0},
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{ TEGRA210_MVC_DURATION_INV, 0x0006d3a0},
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{ TEGRA210_MVC_POLY_N1, 0x0000007d},
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{ TEGRA210_MVC_POLY_N2, 0x00000271},
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{ TEGRA210_MVC_PEAK_CTRL, 0x000012c0},
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{ TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL, 0x00004000},
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};
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static int tegra210_mvc_runtime_suspend(struct device *dev)
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{
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struct tegra210_mvc *mvc = dev_get_drvdata(dev);
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regcache_cache_only(mvc->regmap, true);
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pm_runtime_put_sync(dev->parent);
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return 0;
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}
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static int tegra210_mvc_runtime_resume(struct device *dev)
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{
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struct tegra210_mvc *mvc = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_get_sync(dev->parent);
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if (ret < 0) {
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dev_err(dev, "parent get_sync failed: %d\n", ret);
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return ret;
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}
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regcache_cache_only(mvc->regmap, false);
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regcache_sync(mvc->regmap);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra210_mvc_suspend(struct device *dev)
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{
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struct tegra210_mvc *mvc = dev_get_drvdata(dev);
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regcache_mark_dirty(mvc->regmap);
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return 0;
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}
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#endif
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static int tegra210_mvc_write_ram(struct tegra210_mvc *mvc,
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unsigned int addr,
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unsigned int val)
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{
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unsigned int reg, value, wait = 0xffff;
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/* check if busy */
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do {
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regmap_read(mvc->regmap,
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TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL, &value);
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wait--;
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if (!wait)
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return -EINVAL;
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} while (value & 0x80000000);
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value = 0;
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reg = (addr << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RAM_ADDR_SHIFT) &
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TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RAM_ADDR_MASK;
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reg |= TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_ADDR_INIT_EN;
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reg |= TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RW_WRITE;
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reg |= TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_SEQ_ACCESS_EN;
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regmap_write(mvc->regmap,
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TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL, reg);
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regmap_write(mvc->regmap,
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TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_DATA, val);
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return 0;
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}
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static int tegra210_mvc_get_vol(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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return 0;
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}
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static int tegra210_mvc_put_vol(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct tegra210_mvc *mvc = snd_soc_codec_get_drvdata(codec);
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unsigned int reg = mc->reg;
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unsigned int ret, value, wait = 0xffff;
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/* check if VOLUME_SWITCH is triggered*/
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do {
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regmap_read(mvc->regmap,
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TEGRA210_MVC_SWITCH, &value);
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wait--;
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if (!wait)
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return -EINVAL;
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} while (value & TEGRA210_MVC_VOLUME_SWITCH_MASK);
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if (reg == TEGRA210_MVC_TARGET_VOL) {
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ret = regmap_write(mvc->regmap, TEGRA210_MVC_TARGET_VOL,
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ucontrol->value.integer.value[0]*(1<<24));
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} else {
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ret = regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
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TEGRA210_MVC_MUTE_MASK, (ucontrol->value.integer.value[0] ?
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TEGRA210_MVC_MUTE_EN : 0));
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}
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ret |= regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
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TEGRA210_MVC_VOLUME_SWITCH_MASK,
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TEGRA210_MVC_VOLUME_SWITCH_TRIGGER);
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return ret;
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}
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static int tegra210_mvc_set_audio_cif(struct tegra210_mvc *mvc,
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struct snd_pcm_hw_params *params,
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unsigned int reg)
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{
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int channels, audio_bits;
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struct tegra210_xbar_cif_conf cif_conf;
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channels = params_channels(params);
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if (channels < 2)
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return -EINVAL;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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audio_bits = TEGRA210_AUDIOCIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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audio_bits = TEGRA210_AUDIOCIF_BITS_32;
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break;
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default:
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return -EINVAL;
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}
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cif_conf.threshold = 0;
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cif_conf.audio_channels = channels;
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cif_conf.client_channels = channels;
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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cif_conf.expand = 0;
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cif_conf.stereo_conv = 0;
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cif_conf.replicate = 0;
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cif_conf.truncate = 0;
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cif_conf.mono_conv = 0;
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mvc->soc_data->set_audio_cif(mvc->regmap, reg, &cif_conf);
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return 0;
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}
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static int tegra210_mvc_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra210_mvc *mvc = snd_soc_dai_get_drvdata(dai);
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int i, ret;
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/* set RX cif and TX cif */
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ret = tegra210_mvc_set_audio_cif(mvc, params,
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TEGRA210_MVC_AXBAR_RX_CIF_CTRL);
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if (ret) {
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dev_err(dev, "Can't set MVC RX CIF: %d\n", ret);
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return ret;
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}
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ret = tegra210_mvc_set_audio_cif(mvc, params,
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TEGRA210_MVC_AXBAR_TX_CIF_CTRL);
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if (ret) {
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dev_err(dev, "Can't set MVC TX CIF: %d\n", ret);
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return ret;
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}
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/* disable per_channel_cntrl_en */
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regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
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TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK,
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~(TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK));
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/* init the default volume=1 for MVC */
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regmap_write(mvc->regmap, TEGRA210_MVC_INIT_VOL,
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TEGRA210_MVC_INIT_VOL_DEFAULT);
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/* program the poly coefficients */
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for (i = 0; i < 9; i++)
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tegra210_mvc_write_ram(mvc, i, mvc->poly_coeff[i]);
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/* program poly_n1, poly_n2, duration */
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regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N1, mvc->poly_n1);
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regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N2, mvc->poly_n2);
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regmap_write(mvc->regmap, TEGRA210_MVC_DURATION, mvc->duration);
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/* program duration_inv */
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regmap_write(mvc->regmap, TEGRA210_MVC_DURATION_INV, mvc->duration_inv);
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return ret;
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}
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static int tegra210_mvc_codec_probe(struct snd_soc_codec *codec)
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{
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struct tegra210_mvc *mvc = snd_soc_codec_get_drvdata(codec);
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int ret;
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codec->control_data = mvc->regmap;
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ret = snd_soc_codec_set_cache_io(codec, 64, 32, SND_SOC_REGMAP);
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if (ret != 0) {
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dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static struct snd_soc_dai_ops tegra210_mvc_dai_ops = {
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.hw_params = tegra210_mvc_hw_params,
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};
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static const struct snd_kcontrol_new tegra210_mvc_vol_ctrl[] = {
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SOC_SINGLE_EXT("Vol", TEGRA210_MVC_TARGET_VOL, 0, 100, 0,
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tegra210_mvc_get_vol, tegra210_mvc_put_vol),
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SOC_SINGLE_EXT("Mute", TEGRA210_MVC_CTRL, 0, 1, 0,
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tegra210_mvc_get_vol, tegra210_mvc_put_vol),
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};
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static struct snd_soc_dai_driver tegra210_mvc_dais[] = {
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{
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.name = "MVC IN",
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.playback = {
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.stream_name = "MVC Receive",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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},
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{
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.name = "MVC OUT",
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.capture = {
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.stream_name = "MVC Transmit",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = &tegra210_mvc_dai_ops,
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}
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};
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static const struct snd_soc_dapm_widget tegra210_mvc_widgets[] = {
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SND_SOC_DAPM_AIF_IN("MVC RX", NULL, 0, SND_SOC_NOPM,
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0, 0),
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SND_SOC_DAPM_AIF_OUT("MVC TX", NULL, 0, TEGRA210_MVC_ENABLE,
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TEGRA210_MVC_EN_SHIFT, 0),
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};
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static const struct snd_soc_dapm_route tegra210_mvc_routes[] = {
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{ "MVC RX", NULL, "MVC Receive" },
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{ "MVC TX", NULL, "MVC RX" },
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{ "MVC Transmit", NULL, "MVC TX" },
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};
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static struct snd_soc_codec_driver tegra210_mvc_codec = {
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.probe = tegra210_mvc_codec_probe,
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.dapm_widgets = tegra210_mvc_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra210_mvc_widgets),
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.dapm_routes = tegra210_mvc_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra210_mvc_routes),
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.controls = tegra210_mvc_vol_ctrl,
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.num_controls = ARRAY_SIZE(tegra210_mvc_vol_ctrl),
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.idle_bias_off = 1,
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};
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static bool tegra210_mvc_wr_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_MVC_AXBAR_RX_STATUS:
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case TEGRA210_MVC_AXBAR_RX_INT_STATUS:
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case TEGRA210_MVC_AXBAR_RX_INT_MASK:
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case TEGRA210_MVC_AXBAR_RX_INT_SET:
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case TEGRA210_MVC_AXBAR_RX_INT_CLEAR:
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case TEGRA210_MVC_AXBAR_RX_CIF_CTRL:
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case TEGRA210_MVC_AXBAR_RX_CYA:
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case TEGRA210_MVC_AXBAR_RX_DBG:
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case TEGRA210_MVC_AXBAR_TX_STATUS:
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case TEGRA210_MVC_AXBAR_TX_INT_STATUS:
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case TEGRA210_MVC_AXBAR_TX_INT_MASK:
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case TEGRA210_MVC_AXBAR_TX_INT_SET:
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case TEGRA210_MVC_AXBAR_TX_INT_CLEAR:
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case TEGRA210_MVC_AXBAR_TX_CIF_CTRL:
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case TEGRA210_MVC_AXBAR_TX_CYA:
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case TEGRA210_MVC_AXBAR_TX_DBG:
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case TEGRA210_MVC_ENABLE:
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case TEGRA210_MVC_SOFT_RESET:
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case TEGRA210_MVC_CG:
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case TEGRA210_MVC_STATUS:
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case TEGRA210_MVC_INT_STATUS:
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case TEGRA210_MVC_CTRL:
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case TEGRA210_MVC_SWITCH:
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case TEGRA210_MVC_INIT_VOL:
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case TEGRA210_MVC_TARGET_VOL:
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case TEGRA210_MVC_DURATION:
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case TEGRA210_MVC_DURATION_INV:
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case TEGRA210_MVC_POLY_N1:
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case TEGRA210_MVC_POLY_N2:
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case TEGRA210_MVC_PEAK_CTRL:
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case TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL:
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case TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_MVC_PEAK_VALUE:
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case TEGRA210_MVC_CONFIG_ERR_TYPE:
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case TEGRA210_MVC_CYA:
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case TEGRA210_MVC_DBG:
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return true;
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default:
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return false;
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};
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}
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static bool tegra210_mvc_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_MVC_AXBAR_RX_STATUS:
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case TEGRA210_MVC_AXBAR_RX_INT_STATUS:
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case TEGRA210_MVC_AXBAR_RX_INT_SET:
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case TEGRA210_MVC_AXBAR_TX_STATUS:
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case TEGRA210_MVC_AXBAR_TX_INT_STATUS:
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case TEGRA210_MVC_AXBAR_TX_INT_SET:
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case TEGRA210_MVC_SOFT_RESET:
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case TEGRA210_MVC_STATUS:
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case TEGRA210_MVC_INT_STATUS:
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case TEGRA210_MVC_SWITCH:
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case TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL:
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case TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_MVC_PEAK_VALUE:
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return true;
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default:
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return false;
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};
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}
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static const struct regmap_config tegra210_mvc_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA210_MVC_CYA,
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.writeable_reg = tegra210_mvc_wr_rd_reg,
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.readable_reg = tegra210_mvc_wr_rd_reg,
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.volatile_reg = tegra210_mvc_volatile_reg,
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.reg_defaults = tegra210_mvc_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tegra210_mvc_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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static const struct tegra210_mvc_soc_data soc_data_tegra210 = {
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.set_audio_cif = tegra210_xbar_set_cif,
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};
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static const struct of_device_id tegra210_mvc_of_match[] = {
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{ .compatible = "nvidia,tegra210-mvc", .data = &soc_data_tegra210 },
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{},
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};
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static int tegra210_mvc_platform_probe(struct platform_device *pdev)
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{
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struct tegra210_mvc *mvc;
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struct resource *mem, *memregion;
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void __iomem *regs;
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int ret = 0;
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const struct of_device_id *match;
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struct tegra210_mvc_soc_data *soc_data;
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match = of_match_device(tegra210_mvc_of_match, &pdev->dev);
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if (!match) {
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dev_err(&pdev->dev, "Error: No device match found\n");
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ret = -ENODEV;
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goto err;
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}
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soc_data = (struct tegra210_mvc_soc_data *)match->data;
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mvc = devm_kzalloc(&pdev->dev, sizeof(struct tegra210_mvc), GFP_KERNEL);
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if (!mvc) {
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dev_err(&pdev->dev, "Can't allocate mvc\n");
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ret = -ENOMEM;
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goto err;
|
|
}
|
|
dev_set_drvdata(&pdev->dev, mvc);
|
|
|
|
mvc->soc_data = soc_data;
|
|
|
|
mvc->poly_n1 = 16;
|
|
mvc->poly_n2 = 63;
|
|
mvc->duration = 150;
|
|
mvc->duration_inv = 14316558;
|
|
mvc->poly_coeff[0] = 23738319;
|
|
mvc->poly_coeff[1] = 659403;
|
|
mvc->poly_coeff[2] = -3680;
|
|
mvc->poly_coeff[3] = 15546680;
|
|
mvc->poly_coeff[4] = 2530732;
|
|
mvc->poly_coeff[5] = -120985;
|
|
mvc->poly_coeff[6] = 12048422;
|
|
mvc->poly_coeff[7] = 5527252;
|
|
mvc->poly_coeff[8] = -785042;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mem) {
|
|
dev_err(&pdev->dev, "No memory resource\n");
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
|
|
memregion = devm_request_mem_region(&pdev->dev, mem->start,
|
|
resource_size(mem), pdev->name);
|
|
if (!memregion) {
|
|
dev_err(&pdev->dev, "Memory region already claimed\n");
|
|
ret = -EBUSY;
|
|
goto err;
|
|
}
|
|
|
|
regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
|
|
if (!regs) {
|
|
dev_err(&pdev->dev, "ioremap failed\n");
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
mvc->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
|
&tegra210_mvc_regmap_config);
|
|
if (IS_ERR(mvc->regmap)) {
|
|
dev_err(&pdev->dev, "regmap init failed\n");
|
|
ret = PTR_ERR(mvc->regmap);
|
|
goto err;
|
|
}
|
|
regcache_cache_only(mvc->regmap, true);
|
|
|
|
if (of_property_read_u32(pdev->dev.of_node,
|
|
"nvidia,ahub-mvc-id",
|
|
&pdev->dev.id) < 0) {
|
|
dev_err(&pdev->dev,
|
|
"Missing property nvidia,ahub-mvc-id\n");
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
if (!pm_runtime_enabled(&pdev->dev)) {
|
|
ret = tegra210_mvc_runtime_resume(&pdev->dev);
|
|
if (ret)
|
|
goto err_pm_disable;
|
|
}
|
|
|
|
ret = snd_soc_register_codec(&pdev->dev, &tegra210_mvc_codec,
|
|
tegra210_mvc_dais,
|
|
ARRAY_SIZE(tegra210_mvc_dais));
|
|
if (ret != 0) {
|
|
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
|
|
goto err_suspend;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_suspend:
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra210_mvc_runtime_suspend(&pdev->dev);
|
|
err_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int tegra210_mvc_platform_remove(struct platform_device *pdev)
|
|
{
|
|
snd_soc_unregister_codec(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra210_mvc_runtime_suspend(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra210_mvc_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra210_mvc_runtime_suspend,
|
|
tegra210_mvc_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra210_mvc_suspend, NULL)
|
|
};
|
|
|
|
static struct platform_driver tegra210_mvc_driver = {
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = tegra210_mvc_of_match,
|
|
.pm = &tegra210_mvc_pm_ops,
|
|
},
|
|
.probe = tegra210_mvc_platform_probe,
|
|
.remove = tegra210_mvc_platform_remove,
|
|
};
|
|
module_platform_driver(tegra210_mvc_driver)
|
|
|
|
MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra210 MVC ASoC driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
MODULE_DEVICE_TABLE(of, tegra210_mvc_of_match);
|