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92ac7bc35a
Port camera drivers below from /kenrel/nvidia to /kernel/nvidia-oot as OOT modules: - Fusa-capture driver - Tegra V4L2 framework driver - vi/csi driver - tegra camera platform driver Change-Id: I390af27096425bb11e0934201dd1a90f001bb3fa Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2780698 Reviewed-by: FNU Raunak <fraunak@nvidia.com> Reviewed-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-by: Shiva Dubey <sdubey@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
175 lines
5.5 KiB
C
175 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* TEGRA_V4L2_CAMERA.h - utilities for tegra camera driver
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*
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* Copyright (c) 2017-2022, NVIDIA Corporation. All rights reserved.
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*/
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#ifndef __TEGRA_V4L2_CAMERA__
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#define __TEGRA_V4L2_CAMERA__
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#include <linux/v4l2-controls.h>
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#define TEGRA_CAMERA_CID_BASE (V4L2_CTRL_CLASS_CAMERA | 0x2000)
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#define TEGRA_CAMERA_CID_FRAME_LENGTH (TEGRA_CAMERA_CID_BASE+0)
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#define TEGRA_CAMERA_CID_COARSE_TIME (TEGRA_CAMERA_CID_BASE+1)
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#define TEGRA_CAMERA_CID_COARSE_TIME_SHORT (TEGRA_CAMERA_CID_BASE+2)
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#define TEGRA_CAMERA_CID_GROUP_HOLD (TEGRA_CAMERA_CID_BASE+3)
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#define TEGRA_CAMERA_CID_HDR_EN (TEGRA_CAMERA_CID_BASE+4)
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#define TEGRA_CAMERA_CID_EEPROM_DATA (TEGRA_CAMERA_CID_BASE+5)
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#define TEGRA_CAMERA_CID_OTP_DATA (TEGRA_CAMERA_CID_BASE+6)
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#define TEGRA_CAMERA_CID_FUSE_ID (TEGRA_CAMERA_CID_BASE+7)
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#define TEGRA_CAMERA_CID_SENSOR_MODE_ID (TEGRA_CAMERA_CID_BASE+8)
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#define TEGRA_CAMERA_CID_GAIN (TEGRA_CAMERA_CID_BASE+9)
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#define TEGRA_CAMERA_CID_EXPOSURE (TEGRA_CAMERA_CID_BASE+10)
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#define TEGRA_CAMERA_CID_FRAME_RATE (TEGRA_CAMERA_CID_BASE+11)
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#define TEGRA_CAMERA_CID_EXPOSURE_SHORT (TEGRA_CAMERA_CID_BASE+12)
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#define TEGRA_CAMERA_CID_STEREO_EEPROM (TEGRA_CAMERA_CID_BASE+13)
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#define TEGRA_CAMERA_CID_SENSOR_CONFIG (TEGRA_CAMERA_CID_BASE+50)
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#define TEGRA_CAMERA_CID_SENSOR_MODE_BLOB (TEGRA_CAMERA_CID_BASE+51)
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#define TEGRA_CAMERA_CID_SENSOR_CONTROL_BLOB (TEGRA_CAMERA_CID_BASE+52)
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#define TEGRA_CAMERA_CID_GAIN_TPG (TEGRA_CAMERA_CID_BASE+70)
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#define TEGRA_CAMERA_CID_GAIN_TPG_EMB_DATA_CFG (TEGRA_CAMERA_CID_BASE+71)
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#define TEGRA_CAMERA_CID_VI_BYPASS_MODE (TEGRA_CAMERA_CID_BASE+100)
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#define TEGRA_CAMERA_CID_OVERRIDE_ENABLE (TEGRA_CAMERA_CID_BASE+101)
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#define TEGRA_CAMERA_CID_VI_HEIGHT_ALIGN (TEGRA_CAMERA_CID_BASE+102)
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#define TEGRA_CAMERA_CID_VI_SIZE_ALIGN (TEGRA_CAMERA_CID_BASE+103)
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#define TEGRA_CAMERA_CID_WRITE_ISPFORMAT (TEGRA_CAMERA_CID_BASE+104)
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#define TEGRA_CAMERA_CID_SENSOR_SIGNAL_PROPERTIES (TEGRA_CAMERA_CID_BASE+105)
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#define TEGRA_CAMERA_CID_SENSOR_IMAGE_PROPERTIES (TEGRA_CAMERA_CID_BASE+106)
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#define TEGRA_CAMERA_CID_SENSOR_CONTROL_PROPERTIES (TEGRA_CAMERA_CID_BASE+107)
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#define TEGRA_CAMERA_CID_SENSOR_DV_TIMINGS (TEGRA_CAMERA_CID_BASE+108)
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#define TEGRA_CAMERA_CID_LOW_LATENCY (TEGRA_CAMERA_CID_BASE+109)
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#define TEGRA_CAMERA_CID_VI_PREFERRED_STRIDE (TEGRA_CAMERA_CID_BASE+110)
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/**
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* This is temporary with the current v4l2 infrastructure
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* currently discussing with upstream maintainers our proposals and
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* better approaches to resolve this
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*/
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#define TEGRA_CAMERA_CID_SENSOR_MODES (TEGRA_CAMERA_CID_BASE + 130)
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#define MAX_BUFFER_SIZE 32
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#define MAX_CID_CONTROLS 32
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#define MAX_NUM_SENSOR_MODES 30
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#define OF_MAX_STR_LEN 256
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#define OF_SENSORMODE_PREFIX ("mode")
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/*
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* Scaling factor for converting a Q10.22 fixed point value
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* back to its original floating point value
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*/
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#define FIXED_POINT_SCALING_FACTOR (1ULL << 22)
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#define TEGRA_CAM_MAX_STRING_CONTROLS 8
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#define TEGRA_CAM_STRING_CTRL_EEPROM_INDEX 0
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#define TEGRA_CAM_STRING_CTRL_FUSEID_INDEX 1
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#define TEGRA_CAM_STRING_CTRL_OTP_INDEX 2
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#define TEGRA_CAM_MAX_COMPOUND_CONTROLS 4
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#define TEGRA_CAM_COMPOUND_CTRL_EEPROM_INDEX 0
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#define CSI_PHY_MODE_DPHY 0
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#define CSI_PHY_MODE_CPHY 1
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#define SLVS_EC 2
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struct unpackedU64 {
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__u32 high;
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__u32 low;
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};
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union __u64val {
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struct unpackedU64 unpacked;
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__u64 val;
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};
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struct sensor_signal_properties {
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__u32 readout_orientation;
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__u32 num_lanes;
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__u32 mclk_freq;
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union __u64val pixel_clock;
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__u32 cil_settletime;
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__u32 discontinuous_clk;
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__u32 dpcm_enable;
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__u32 tegra_sinterface;
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__u32 phy_mode;
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__u32 deskew_initial_enable;
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__u32 deskew_periodic_enable;
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union __u64val serdes_pixel_clock;
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union __u64val mipi_clock;
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};
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struct sensor_image_properties {
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__u32 width;
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__u32 height;
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__u32 line_length;
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__u32 pixel_format;
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__u32 embedded_metadata_height;
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__u32 reserved[11];
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};
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struct sensor_dv_timings {
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__u32 hfrontporch;
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__u32 hsync;
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__u32 hbackporch;
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__u32 vfrontporch;
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__u32 vsync;
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__u32 vbackporch;
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__u32 reserved[10];
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};
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struct sensor_control_properties {
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__u32 gain_factor;
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__u32 framerate_factor;
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__u32 inherent_gain;
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__u32 min_gain_val;
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__u32 max_gain_val;
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__u32 min_hdr_ratio;
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__u32 max_hdr_ratio;
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__u32 min_framerate;
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__u32 max_framerate;
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union __u64val min_exp_time;
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union __u64val max_exp_time;
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__u32 step_gain_val;
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__u32 step_framerate;
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__u32 exposure_factor;
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union __u64val step_exp_time;
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__u32 default_gain;
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__u32 default_framerate;
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union __u64val default_exp_time;
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__u32 is_interlaced;
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__u32 interlace_type;
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__u32 reserved[10];
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};
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struct sensor_mode_properties {
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struct sensor_signal_properties signal_properties;
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struct sensor_image_properties image_properties;
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struct sensor_control_properties control_properties;
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struct sensor_dv_timings dv_timings;
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};
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#define SENSOR_SIGNAL_PROPERTIES_CID_SIZE \
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(sizeof(struct sensor_signal_properties) / sizeof(__u32))
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#define SENSOR_IMAGE_PROPERTIES_CID_SIZE \
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(sizeof(struct sensor_image_properties) / sizeof(__u32))
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#define SENSOR_CONTROL_PROPERTIES_CID_SIZE \
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(sizeof(struct sensor_control_properties) / sizeof(__u32))
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#define SENSOR_DV_TIMINGS_CID_SIZE \
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(sizeof(struct sensor_dv_timings) / sizeof(__u32))
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#define SENSOR_MODE_PROPERTIES_CID_SIZE \
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(sizeof(struct sensor_mode_properties) / sizeof(__u32))
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#define SENSOR_CONFIG_SIZE \
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(sizeof(struct sensor_cfg) / sizeof(__u32))
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#define SENSOR_MODE_BLOB_SIZE \
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(sizeof(struct sensor_blob) / sizeof(__u32))
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#define SENSOR_CTRL_BLOB_SIZE \
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(sizeof(struct sensor_blob) / sizeof(__u32))
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#endif /* __TEGRA_V4L2_CAMERA__ */
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