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git://nv-tegra.nvidia.com/linux-nv-oot.git
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0daf056dc9
Use SPDX license GPL-V2.0 format and change Nvidia copyright year to include 2023. Bug 4078035 Change-Id: If13a0a9309c76e1e7b53d6967eada9ed321b8e93 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2890633 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Tegra TSEC Module Support
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*/
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#ifndef TSEC_BOOT_H
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#define TSEC_BOOT_H
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#define RISCV_IDLE_TIMEOUT_DEFAULT 100000 /* 100 milliseconds */
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#define RISCV_IDLE_TIMEOUT_LONG 2000000 /* 2 seconds */
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#define RISCV_IDLE_CHECK_PERIOD 10 /* 10 usec */
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#define RISCV_IDLE_CHECK_PERIOD_LONG 1000 /* 1 milliseconds */
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/* Image descriptor format */
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struct RM_RISCV_UCODE_DESC {
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/*
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* Version 1
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* Version 2
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* Vesrion 3 = for Partition boot
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* Vesrion 4 = for eb riscv boot
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*/
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u32 version; /* structure version */
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u32 bootloaderOffset;
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u32 bootloaderSize;
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u32 bootloaderParamOffset;
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u32 bootloaderParamSize;
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u32 riscvElfOffset;
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u32 riscvElfSize;
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u32 appVersion; /* Changelist number associated with the image */
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/*
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* Manifest contains information about Monitor and it is
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* input to BR
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*/
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u32 manifestOffset;
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u32 manifestSize;
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/*
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* Monitor Data offset within RISCV image and size
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*/
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u32 monitorDataOffset;
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u32 monitorDataSize;
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/*
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* Monitor Code offset withtin RISCV image and size
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*/
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u32 monitorCodeOffset;
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u32 monitorCodeSize;
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u32 bIsMonitorEnabled;
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/*
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* Swbrom Code offset within RISCV image and size
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*/
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u32 swbromCodeOffset;
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u32 swbromCodeSize;
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/*
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* Swbrom Data offset within RISCV image and size
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*/
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u32 swbromDataOffset;
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u32 swbromDataSize;
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};
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struct riscv_image_desc {
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u32 manifest_offset;
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u32 manifest_size;
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u32 data_offset;
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u32 data_size;
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u32 code_offset;
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u32 code_size;
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};
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struct riscv_data {
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bool valid;
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struct riscv_image_desc desc;
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dma_addr_t backdoor_img_iova;
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u32 *backdoor_img_va;
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size_t backdoor_img_size;
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};
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int tsec_kickoff_boot(struct platform_device *pdev);
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int tsec_finalize_poweron(struct platform_device *dev);
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int tsec_prepare_poweroff(struct platform_device *dev);
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#endif /* TSEC_BOOT_H */
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