mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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c4ab6f5a0e
PEQ and MBDRC are sub blocks of OPE module. So far, these sub blocks were not represented by separate device nodes in DT. This has changed now where PEQ and MBDRC are children of OPE block. For now the driver structure is maintained as it is and explicitly parse PEQ and MBDRC nodes to create corresponding regmap interfaces. With this there is flexibility now to create separate device drivers for PEQ and MBDRC if necessary in future. Bug 3583581 Change-Id: I16ceb9b1a30b4ddb1a57fdef28db20c554c58b03 Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2783022 Reviewed-by: Mohan Kumar D <mkumard@nvidia.com> Reviewed-by: Sharad Gupta <sharadg@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
398 lines
12 KiB
C
398 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// tegra210_peq.c - Tegra210 PEQ driver
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//
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// Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "tegra210_ahub.h"
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#include "tegra210_ope.h"
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#include "tegra210_peq.h"
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static const struct reg_default tegra210_peq_reg_defaults[] = {
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{ TEGRA210_PEQ_CONFIG, 0x00000013},
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{ TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL, 0x00004000},
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{ TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL, 0x00004000},
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};
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/* Default PEQ filter parameters for a 5-stage biquad*/
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static const int biquad_init_stage = 5;
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static const u32 biquad_init_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH] = {
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1495012349, /* pre-gain */
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/* Gains : b0, b1, a0, a1, a2 */
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536870912, -1073741824, 536870912, 2143508246, -1069773768, /* band-0 */
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134217728, -265414508, 131766272, 2140402222, -1071252997, /* band-1 */
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268435456, -233515765, -33935948, 1839817267, -773826124, /* band-2 */
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536870912, -672537913, 139851540, 1886437554, -824433167, /* band-3 */
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268435456, -114439279, 173723964, 205743566, 278809729, /* band-4 */
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1, 0, 0, 0, 0, /* band-5 */
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1, 0, 0, 0, 0, /* band-6 */
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1, 0, 0, 0, 0, /* band-7 */
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1, 0, 0, 0, 0, /* band-8 */
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1, 0, 0, 0, 0, /* band-9 */
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1, 0, 0, 0, 0, /* band-10 */
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1, 0, 0, 0, 0, /* band-11 */
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963423114, /* post-gain */
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};
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static const u32 biquad_init_shifts[TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH] = {
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23, /* pre-shift */
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30, 30, 30, 30, 30, 0, 0, 0, 0, 0, 0, 0, /* shift for bands */
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28, /* post-shift */
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};
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static s32 biquad_coeff_buffer[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH];
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static int tegra210_peq_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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unsigned int mask = (1 << fls(mc->max)) - 1;
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unsigned int val;
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regmap_read(ope->peq_regmap, mc->reg, &val);
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ucontrol->value.integer.value[0] = (val >> mc->shift) & mask;
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if (mc->invert)
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ucontrol->value.integer.value[0] =
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mc->max - ucontrol->value.integer.value[0];
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return 0;
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}
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static int tegra210_peq_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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unsigned int mask = (1 << fls(mc->max)) - 1;
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unsigned int val;
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val = (ucontrol->value.integer.value[0] & mask);
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if (mc->invert)
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val = mc->max - val;
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val = val << mc->shift;
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return regmap_update_bits(ope->peq_regmap, mc->reg,
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(mask << mc->shift), val);
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}
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static int tegra210_peq_ahub_ram_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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u32 i, reg_ctrl = params->soc.base;
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u32 reg_data = reg_ctrl + cmpnt->val_bytes;
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s32 *data = (s32 *)biquad_coeff_buffer;
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pm_runtime_get_sync(cmpnt->dev);
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tegra210_ahub_read_ram(ope->peq_regmap, reg_ctrl, reg_data,
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params->shift, data, params->soc.num_regs);
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pm_runtime_put_sync(cmpnt->dev);
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for (i = 0; i < params->soc.num_regs; i++)
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ucontrol->value.integer.value[i] = (long)data[i];
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return 0;
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}
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static int tegra210_peq_ahub_ram_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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u32 i, reg_ctrl = params->soc.base;
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u32 reg_data = reg_ctrl + cmpnt->val_bytes;
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s32 *data = (s32 *)biquad_coeff_buffer;
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for (i = 0; i < params->soc.num_regs; i++)
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data[i] = (s32)ucontrol->value.integer.value[i];
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pm_runtime_get_sync(cmpnt->dev);
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tegra210_ahub_write_ram(ope->peq_regmap, reg_ctrl, reg_data,
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params->shift, data, params->soc.num_regs);
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pm_runtime_put_sync(cmpnt->dev);
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return 0;
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}
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static int tegra210_peq_param_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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struct soc_bytes *params = (void *)kcontrol->private_value;
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uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
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uinfo->value.integer.min = -0x7fffffff;
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uinfo->value.integer.max = 0x7fffffff;
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uinfo->count = params->num_regs;
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return 0;
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}
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#define TEGRA210_PEQ_GAIN_PARAMS_CTRL(chan) \
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TEGRA_SOC_BYTES_EXT("peq channel" #chan " biquad gain params", \
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL, \
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH, \
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(TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH * chan), 0xffffffff, \
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tegra210_peq_ahub_ram_get, tegra210_peq_ahub_ram_put, \
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tegra210_peq_param_info)
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#define TEGRA210_PEQ_SHIFT_PARAMS_CTRL(chan) \
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TEGRA_SOC_BYTES_EXT("peq channel" #chan " biquad shift params", \
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL, \
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH, \
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(TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH * chan), 0x1f, \
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tegra210_peq_ahub_ram_get, tegra210_peq_ahub_ram_put, \
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tegra210_peq_param_info)
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static const struct snd_kcontrol_new tegra210_peq_controls[] = {
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SOC_SINGLE_EXT("peq active", TEGRA210_PEQ_CONFIG,
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TEGRA210_PEQ_CONFIG_MODE_SHIFT, 1, 0,
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tegra210_peq_get, tegra210_peq_put),
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SOC_SINGLE_EXT("peq biquad stages", TEGRA210_PEQ_CONFIG,
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TEGRA210_PEQ_CONFIG_BIQUAD_STAGES_SHIFT,
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TEGRA210_PEQ_MAX_BIQUAD_STAGES - 1, 0,
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tegra210_peq_get, tegra210_peq_put),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(0),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(1),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(2),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(3),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(4),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(5),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(6),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(7),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(0),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(1),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(2),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(3),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(4),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(5),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(6),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(7),
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};
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static bool tegra210_peq_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_SOFT_RESET:
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case TEGRA210_PEQ_CG:
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case TEGRA210_PEQ_CONFIG:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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}
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}
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static bool tegra210_peq_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_SOFT_RESET:
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case TEGRA210_PEQ_CG:
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case TEGRA210_PEQ_STATUS:
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case TEGRA210_PEQ_CONFIG:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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}
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}
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static bool tegra210_peq_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_SOFT_RESET:
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case TEGRA210_PEQ_STATUS:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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}
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}
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static bool tegra210_peq_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA:
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case TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config tegra210_peq_regmap_config = {
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.name = "peq",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA,
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.writeable_reg = tegra210_peq_wr_reg,
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.readable_reg = tegra210_peq_rd_reg,
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.volatile_reg = tegra210_peq_volatile_reg,
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.precious_reg = tegra210_peq_precious_reg,
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.reg_defaults = tegra210_peq_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tegra210_peq_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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void tegra210_peq_restore(struct tegra210_ope *ope)
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{
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unsigned int i;
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for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
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tegra210_ahub_write_ram(ope->peq_regmap,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA,
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(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
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(u32 *)&ope->peq_biquad_gains,
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
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tegra210_ahub_write_ram(ope->peq_regmap,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA,
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(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
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(u32 *)&ope->peq_biquad_shifts,
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
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}
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}
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EXPORT_SYMBOL_GPL(tegra210_peq_restore);
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void tegra210_peq_save(struct tegra210_ope *ope)
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{
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unsigned int i;
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for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
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tegra210_ahub_read_ram(ope->peq_regmap,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA,
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(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
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(u32 *)&ope->peq_biquad_gains,
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
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tegra210_ahub_read_ram(ope->peq_regmap,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA,
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(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
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(u32 *)&ope->peq_biquad_shifts,
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
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}
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}
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EXPORT_SYMBOL_GPL(tegra210_peq_save);
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int tegra210_peq_codec_init(struct snd_soc_component *cmpnt)
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{
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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int i = 0;
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pm_runtime_get_sync(cmpnt->dev);
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regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CONFIG,
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TEGRA210_PEQ_CONFIG_MODE_MASK,
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0 << TEGRA210_PEQ_CONFIG_MODE_SHIFT);
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regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CONFIG,
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TEGRA210_PEQ_CONfIG_BIQUAD_STAGES_MASK,
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(biquad_init_stage - 1) <<
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TEGRA210_PEQ_CONFIG_BIQUAD_STAGES_SHIFT);
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/* Initialize PEQ AHUB RAM with default params */
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for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
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/* Set default gain params */
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tegra210_ahub_write_ram(ope->peq_regmap,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA,
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(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
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(u32 *)&biquad_init_gains,
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
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/* Set default shift params */
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tegra210_ahub_write_ram(ope->peq_regmap,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL,
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TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA,
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(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
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(u32 *)&biquad_init_shifts,
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
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}
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pm_runtime_put_sync(cmpnt->dev);
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snd_soc_add_component_controls(cmpnt, tegra210_peq_controls,
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ARRAY_SIZE(tegra210_peq_controls));
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra210_peq_codec_init);
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int tegra210_peq_regmap_init(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct tegra210_ope *ope = dev_get_drvdata(dev);
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struct device_node *child;
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struct resource mem;
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void __iomem *regs;
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int err;
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child = of_get_child_by_name(dev->of_node, "equalizer");
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if (!child)
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return -ENODEV;
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err = of_address_to_resource(child, 0, &mem);
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of_node_put(child);
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if (err < 0) {
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dev_err(dev, "fail to get PEQ resource\n");
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return err;
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}
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mem.flags = IORESOURCE_MEM;
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regs = devm_ioremap_resource(dev, &mem);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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ope->peq_regmap = devm_regmap_init_mmio(dev, regs,
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&tegra210_peq_regmap_config);
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if (IS_ERR(ope->peq_regmap)) {
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dev_err(dev, "regmap init failed\n");
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return PTR_ERR(ope->peq_regmap);
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}
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regcache_cache_only(ope->peq_regmap, true);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra210_peq_regmap_init);
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MODULE_AUTHOR("Sumit Bhattacharya <sumitb@nvidia.com>");
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MODULE_DESCRIPTION("Tegra210 PEQ module");
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MODULE_LICENSE("GPL");
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