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IRQ is external interface for DMA driver. Use one IRQ handler callbacks to register and call SoC specific handler them based on SoC type. Add ICD documentation for common IRQ API's JIRA NET-2663 Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Change-Id: I51137489ebe071e2e4a3edc3c5e3fefb84c994fa Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3305091 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
152 lines
4.4 KiB
C
152 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* SPDX-FileCopyrightText: Copyright (c) 2024-2025, NVIDIA CORPORATION. All rights reserved. */
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#ifndef TEGRA234_PCIE_EDMA_OSI_H
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#define TEGRA234_PCIE_EDMA_OSI_H
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#undef OSI_BIT
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#define OSI_BIT(b) (1U << (b))
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/** generates bit mask for 32 bit value */
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#undef OSI_GENMASK
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#define OSI_GENMASK(h, l) (((~0U) << (l)) & (~0U >> (31U - (h))))
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/* Channel specific registers */
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#define DMA_CH_CONTROL1_OFF_WRCH 0x0
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#define DMA_CH_CONTROL1_OFF_WRCH_LLE OSI_BIT(9)
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#define DMA_CH_CONTROL1_OFF_WRCH_CCS OSI_BIT(8)
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#define DMA_CH_CONTROL1_OFF_WRCH_CS_MASK OSI_GENMASK(6U, 5U)
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#define DMA_CH_CONTROL1_OFF_WRCH_CS_SHIFT 5
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#define DMA_CH_CONTROL1_OFF_WRCH_RIE OSI_BIT(4)
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#define DMA_CH_CONTROL1_OFF_WRCH_LIE OSI_BIT(3)
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#define DMA_CH_CONTROL1_OFF_WRCH_LLP OSI_BIT(2)
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#define DMA_CH_CONTROL1_OFF_WRCH_CB OSI_BIT(0)
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#define DMA_WRITE_ENGINE_EN_OFF 0xC
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#define WRITE_ENABLE OSI_BIT(0)
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#define WRITE_DISABLE 0x0
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#define DMA_WRITE_DOORBELL_OFF 0x10
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#define DMA_WRITE_DOORBELL_OFF_WR_STOP OSI_BIT(31)
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#define DMA_READ_ENGINE_EN_OFF 0x2C
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#define READ_ENABLE OSI_BIT(0)
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#define READ_DISABLE 0x0
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#define DMA_READ_DOORBELL_OFF 0x30
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#define DMA_READ_DOORBELL_OFF_RD_STOP OSI_BIT(31)
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#define DMA_TRANSFER_SIZE_OFF_WRCH 0x8
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#define DMA_SAR_LOW_OFF_WRCH 0xC
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#define DMA_SAR_HIGH_OFF_WRCH 0x10
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#define DMA_DAR_LOW_OFF_WRCH 0x14
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#define DMA_DAR_HIGH_OFF_WRCH 0x18
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#define DMA_LLP_LOW_OFF_WRCH 0x1C
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#define DMA_LLP_HIGH_OFF_WRCH 0x20
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#define DMA_WRITE_DONE_IMWR_LOW_OFF 0x60
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#define DMA_WRITE_DONE_IMWR_HIGH_OFF 0x64
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#define DMA_WRITE_ABORT_IMWR_LOW_OFF 0x68
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#define DMA_WRITE_ABORT_IMWR_HIGH_OFF 0x6c
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#define DMA_WRITE_CH01_IMWR_DATA_OFF 0x70
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#define DMA_WRITE_CH23_IMWR_DATA_OFF 0x74
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#define DMA_WRITE_LINKED_LIST_ERR_EN_OFF 0x90
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#define DMA_READ_LINKED_LIST_ERR_EN_OFF 0xC4
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#define DMA_READ_DONE_IMWR_LOW_OFF 0xcc
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#define DMA_READ_DONE_IMWR_HIGH_OFF 0xd0
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#define DMA_READ_ABORT_IMWR_LOW_OFF 0xd4
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#define DMA_READ_ABORT_IMWR_HIGH_OFF 0xd8
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#define DMA_READ_CH01_IMWR_DATA_OFF 0xdc
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#define DMA_CH_CONTROL1_OFF_RDCH 0x100
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#define DMA_CH_CONTROL1_OFF_RDCH_LLE OSI_BIT(9)
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#define DMA_CH_CONTROL1_OFF_RDCH_CCS OSI_BIT(8)
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#define DMA_CH_CONTROL1_OFF_RDCH_CS_MASK OSI_GENMASK(6U, 5U)
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#define DMA_CH_CONTROL1_OFF_RDCH_CS_SHIFT 5
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#define DMA_CH_CONTROL1_OFF_RDCH_RIE OSI_BIT(4)
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#define DMA_CH_CONTROL1_OFF_RDCH_LIE OSI_BIT(3)
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#define DMA_CH_CONTROL1_OFF_RDCH_LLP OSI_BIT(2)
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#define DMA_CH_CONTROL1_OFF_RDCH_CB OSI_BIT(0)
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#define DMA_TRANSFER_SIZE_OFF_RDCH 0x108
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#define DMA_SAR_LOW_OFF_RDCH 0x10c
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#define DMA_SAR_HIGH_OFF_RDCH 0x110
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#define DMA_DAR_LOW_OFF_RDCH 0x114
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#define DMA_DAR_HIGH_OFF_RDCH 0x118
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#define DMA_LLP_LOW_OFF_RDCH 0x11c
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#define DMA_LLP_HIGH_OFF_RDCH 0x120
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#define DMA_WRITE_INT_STATUS_OFF 0x4C
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#define DMA_WRITE_INT_MASK_OFF 0x54
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#define DMA_WRITE_INT_CLEAR_OFF 0x58
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#define DMA_READ_INT_STATUS_OFF 0xA0
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#define DMA_READ_INT_MASK_OFF 0xA8
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#define DMA_READ_INT_CLEAR_OFF 0xAC
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struct edma_ctrl {
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uint32_t cb:1;
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uint32_t tcb:1;
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uint32_t llp:1;
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uint32_t lie:1;
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uint32_t rie:1;
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};
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struct edma_hw_desc {
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volatile union {
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struct edma_ctrl ctrl_e;
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uint32_t ctrl_d;
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} ctrl_reg;
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uint32_t size;
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uint32_t sar_low;
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uint32_t sar_high;
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uint32_t dar_low;
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uint32_t dar_high;
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};
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struct edma_hw_desc_llp {
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volatile union {
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struct edma_ctrl ctrl_e;
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uint32_t ctrl_d;
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} ctrl_reg;
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uint32_t size;
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uint32_t sar_low;
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uint32_t sar_high;
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};
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struct edma_dblock {
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struct edma_hw_desc desc[2];
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struct edma_hw_desc_llp llp;
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};
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static inline unsigned int dma_common_rd(void __iomem *p, unsigned int offset)
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{
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return readl(p + offset);
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}
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static inline void dma_common_wr(void __iomem *p, unsigned int val, unsigned int offset)
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{
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writel(val, p + offset);
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}
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static inline void dma_channel_wr(void __iomem *p, unsigned char c, unsigned int val, u32 offset)
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{
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writel(val, (0x200 * (c + 1)) + p + offset);
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}
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static inline unsigned int dma_channel_rd(void __iomem *p, unsigned char c, u32 offset)
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{
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return readl((0x200 * (c + 1)) + p + offset);
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}
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irqreturn_t edma_irq(int irq, void *cookie);
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irqreturn_t edma_irq_handler(int irq, void *cookie);
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void *tegra234_pcie_edma_initialize(struct tegra_pcie_dma_init_info *info, void *priv_dma);
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tegra_pcie_dma_status_t tegra234_pcie_edma_submit_xfer(void *cookie,
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struct tegra_pcie_dma_xfer_info *tx_info);
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bool tegra234_pcie_edma_stop(void *cookie);
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void tegra234_pcie_edma_deinit(void *cookie, void *priv_dma);
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#endif // TEGRA234_PCIE_EDMA_OSI_H
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