mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-23 17:55:05 +03:00
ad95189d09
Add clock, reset and stream-id header files and include them in the overlay dts. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Change-Id: I1835cff21c34b143e58ead405af7f64bd9a6cb89 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2763002 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
251 lines
7.8 KiB
C
251 lines
7.8 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This file contains list of SMMU Stream IDs used in Tegra234.
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*/
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#ifndef _DT_BINDINGS_MEMORY_TEGRA234_SMMU_STREAMID_H
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#define _DT_BINDINGS_MEMORY_TEGRA234_SMMU_STREAMID_H
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/*
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********* ISO SMMU STREAM IDs ***********
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*/
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#define TEGRA234_SID_ISO_NVDISPLAY 0x1U
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#define TEGRA_SID_ISO_VI 0x2U
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#define TEGRA234_SID_ISO_VIFALC 0x3U
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#define TEGRA234_SID_ISO_VI2 0x4U
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#define TEGRA234_SID_ISO_VI2FALC 0x5U
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#define TEGRA234_SID_VI_VM2 0x6U
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#define TEGRA234_SID_VI2_VM2 0x7U
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/*
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********* NISO0 SMMU STREAM IDs **********
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*/
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#define TEGRA234_SID_AON 0x1U
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#define TEGRA234_SID_ETR 0x5U
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#define TEGRA234_SID_NVDISPLAY 0x7U
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#define TEGRA234_SID_DCE 0x8U
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#define TEGRA234_SID_PSC 0x9U
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#define TEGRA234_SID_RCE 0xAU
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#define TEGRA234_SID_SCE 0xBU
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#define TEGRA234_SID_UFSHC 0xCU
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#define TEGRA234_SID_APE_1 0xDU
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/* The GPC DMA clients. */
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#define TEGRA234_SID_GPCDMA_1 0xEU
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#define TEGRA234_SID_GPCDMA_2 0xFU
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#define TEGRA234_SID_GPCDMA_3 0x10U
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#define TEGRA234_SID_GPCDMA_4 0x11U
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#define TEGRA234_SID_RCE_VM2 0x16U
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#define TEGRA234_SID_RCE_SERVER 0x17U
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#define TEGRA234_SID_SMMU_TEST 0x18U
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/* UFS virtual SIDs for storage clients */
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#define TEGRA234_SID_UFS_1 0x19U
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#define TEGRA234_SID_UFS_2 0x1AU
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#define TEGRA234_SID_UFS_3 0x1BU
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#define TEGRA234_SID_UFS_4 0x1CU
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#define TEGRA234_SID_UFS_5 0x1DU
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#define TEGRA234_SID_UFS_6 0x1EU
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#define TEGRA234_SID_NVDLA1 0x23U
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#define TEGRA234_SID_NVENC 0x24U
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#define TEGRA234_SID_NVJPG1 0x25U
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#define TEGRA234_SID_OFA 0x26U
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/* Reserved streamid corrosponding to NISO1 host1x clients */
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#define TEGRA234_SID_NISO1_RESV0 0x27U
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#define TEGRA234_SID_NISO1_RESV1 0x28U
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#define TEGRA234_SID_NISO1_RESV2 0x29U
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#define TEGRA234_SID_NISO1_RESV3 0x2AU
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#define TEGRA234_SID_NISO1_RESV4 0x2BU
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#define TEGRA234_SID_NISO1_RESV5 0x2CU
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#define TEGRA234_SID_NISO1_RESV6 0x2DU
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#define TEGRA234_SID_NISO1_RESV7 0x2EU
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#define TEGRA234_SID_NISO1_RESV8 0x2FU
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#define TEGRA234_SID_NISO1_RESV9 0x30U
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#define TEGRA234_SID_NISO1_RESV10 0x31U
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#define TEGRA234_SID_NISO1_RESV11 0x32U
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#define TEGRA234_SID_NISO1_RESV12 0x33U
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#define TEGRA234_SID_NISO1_RESV13 0x34U
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/* Host1x virtualization clients. */
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#define TEGRA234_SID_HOST1X_CTX0 0x35U
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#define TEGRA234_SID_HOST1X_CTX1 0x36U
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#define TEGRA234_SID_HOST1X_CTX2 0x37U
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#define TEGRA234_SID_HOST1X_CTX3 0x38U
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#define TEGRA234_SID_HOST1X_CTX4 0x39U
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#define TEGRA234_SID_HOST1X_CTX5 0x3AU
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#define TEGRA234_SID_HOST1X_CTX6 0x3BU
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#define TEGRA234_SID_HOST1X_CTX7 0x3CU
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/* Reserved streamid corrosponding to NISO1 host1x clients */
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#define TEGRA234_SID_RESV14 0x3DU
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#define TEGRA234_SID_RESV15 0x3EU
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#define TEGRA234_SID_RESV16 0x3FU
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#define TEGRA234_SID_RESV17 0x40U
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#define TEGRA234_SID_RESV18 0x41U
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#define TEGRA234_SID_RESV19 0x42U
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#define TEGRA234_SID_RESV20 0x43U
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#define TEGRA234_SID_RESV21 0x44U
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#define TEGRA234_SID_RESV22 0x45U
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#define TEGRA234_SID_RESV23 0x46U
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#define TEGRA234_SID_RESV24 0x47U
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#define TEGRA234_SID_RESV25 0x48U
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/* MGBE virtualization clients. */
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#define TEGRA234_SID_MGBE_VF4 0x4CU
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#define TEGRA234_SID_MGBE_VF5 0x4DU
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#define TEGRA234_SID_MGBE_VF6 0x4EU
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#define TEGRA234_SID_MGBE_VF7 0x4FU
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#define TEGRA234_SID_MGBE_VF8 0x50U
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#define TEGRA234_SID_MGBE_VF9 0x51U
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#define TEGRA234_SID_MGBE_VF10 0x52U
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#define TEGRA234_SID_MGBE_VF11 0x53U
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#define TEGRA234_SID_MGBE_VF12 0x54U
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#define TEGRA234_SID_MGBE_VF13 0x55U
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#define TEGRA234_SID_MGBE_VF14 0x56U
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#define TEGRA234_SID_MGBE_VF15 0x57U
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#define TEGRA234_SID_MGBE_VF16 0x58U
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#define TEGRA234_SID_MGBE_VF17 0x59U
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#define TEGRA234_SID_MGBE_VF18 0x5AU
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#define TEGRA234_SID_MGBE_VF19 0x5BU
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#define TEGRA234_SID_MGBE_VF20 0x5CU
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/* FIXME: Hack to support FSI Client on VDK */
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#define TEGRA234_SID_VDK_FSI 0x5DU
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/* Additional APE stream-ids */
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#define TEGRA234_SID_APE_2 0x5EU
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#define TEGRA234_SID_APE_3 0x5FU
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/* UFS virtual SIDs for storage clients (extra SIDs) */
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#define TEGRA234_SID_UFS_7 0x60
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#define TEGRA234_SID_UFS_8 0x61
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#define TEGRA234_SID_UFS_9 0x62
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#define TEGRA234_SID_UFS_10 0x63
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#define TEGRA234_SID_UFS_11 0x64
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#define TEGRA234_SID_UFS_12 0x65
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#define TEGRA234_SID_UFS_13 0x66
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#define TEGRA234_SID_UFS_14 0x67
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#define TEGRA234_SID_UFS_15 0x68
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#define TEGRA234_SID_UFS_16 0x69
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#define TEGRA234_SID_UFS_17 0x6A
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#define TEGRA234_SID_UFS_18 0x6B
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#define TEGRA234_SID_UFS_19 0x6C
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#define TEGRA234_SID_UFS_20 0x6D
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/* Additional SIDs for GPC DMA clients. */
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#define TEGRA234_SID_GPCDMA_5 0x6EU
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#define TEGRA234_SID_GPCDMA_6 0x6FU
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#define TEGRA234_SID_GPCDMA_7 0x70U
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#define TEGRA234_SID_GPCDMA_8 0x71U
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#define TEGRA234_SID_GPCDMA_9 0x72U
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#define TEGRA234_SID_GPCDMA_10 0x73U
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#define TEGRA234_SID_GPCDMA_11 0x74U
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#define TEGRA234_SID_GPCDMA_12 0x75U
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/*
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********* NISO1 SMMU STREAM IDs **********
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*/
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#define TEGRA234_SID_SDMMC1A 0x1U
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#define TEGRA234_SID_EQOS 0x3U
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#define TEGRA234_SID_HWMP_PMA 0x4U
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#define TEGRA234_SID_QSPI0 0xCU
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#define TEGRA234_SID_QSPI1 0xDU
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#define TEGRA234_SID_XUSB_HOST 0xEU
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#define TEGRA234_SID_XUSB_DEV 0xFU
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#define TEGRA234_SID_NISO1_FSI 0x11U
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/* PVA virtualization clients. */
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#define TEGRA234_SID_PVA0_VM0 0x12U
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#define TEGRA234_SID_PVA0_VM1 0x13U
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#define TEGRA234_SID_PVA0_VM2 0x14U
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#define TEGRA234_SID_PVA0_VM3 0x15U
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#define TEGRA234_SID_PVA0_VM4 0x16U
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#define TEGRA234_SID_PVA0_VM5 0x17U
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#define TEGRA234_SID_PVA0_VM6 0x18U
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#define TEGRA234_SID_PVA0_VM7 0x19U
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#define TEGRA234_SID_XUSB_VF0 0x1AU
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#define TEGRA234_SID_XUSB_VF1 0x1BU
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#define TEGRA234_SID_XUSB_VF2 0x1CU
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#define TEGRA234_SID_XUSB_VF3 0x1DU
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/* EQOS virtual functions */
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#define TEGRA234_SID_EQOS_VF1 0x1EU
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#define TEGRA234_SID_EQOS_VF2 0x1FU
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#define TEGRA234_SID_EQOS_VF3 0x20U
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#define TEGRA234_SID_EQOS_VF4 0x21U
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#define TEGRA234_SID_ISP_VM2 0x22U
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/* Reserved streamid corrosponding to NISO0 host1x clients */
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#define TEGRA234_SID_NISO0_RESV0 0x23U
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#define TEGRA234_SID_NISO0_RESV1 0x24U
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#define TEGRA234_SID_NISO0_RESV2 0x25U
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#define TEGRA234_SID_NISO0_RESV3 0x26U
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#define TEGRA234_SID_HC 0x27U
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#define TEGRA234_SID_ISP 0x28U
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#define TEGRA234_SID_NVDEC 0x29U
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#define TEGRA234_SID_NVJPG 0x2AU
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#define TEGRA234_SID_NVDLA0 0x2BU
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#define TEGRA234_SID_PVA0 0x2CU
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#define TEGRA234_SID_SES_SE0 0x2DU
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#define TEGRA234_SID_SES_SE1 0x2EU
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#define TEGRA234_SID_SES_SE2 0x2FU
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#define TEGRA234_SID_SEU1_SE0 0x30U
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#define TEGRA234_SID_SEU1_SE1 0x31U
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#define TEGRA234_SID_SEU1_SE2 0x32U
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#define TEGRA234_SID_TSEC 0x33U
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/* Host1x virtualization clients. */
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#define TEGRA234_SID_HOST1X_CTX1 0x36U
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#define TEGRA234_SID_HOST1X_CTX2 0x37U
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#define TEGRA234_SID_HOST1X_CTX3 0x38U
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#define TEGRA234_SID_HOST1X_CTX4 0x39U
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#define TEGRA234_SID_HOST1X_CTX5 0x3AU
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#define TEGRA234_SID_HOST1X_CTX6 0x3BU
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#define TEGRA234_SID_HOST1X_CTX7 0x3CU
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/* Host1x command buffers */
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#define TEGRA234_SID_HC_VM0 0x3DU
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#define TEGRA234_SID_HC_VM1 0x3EU
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#define TEGRA234_SID_HC_VM2 0x3FU
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#define TEGRA234_SID_HC_VM3 0x40U
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#define TEGRA234_SID_HC_VM4 0x41U
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#define TEGRA234_SID_HC_VM5 0x42U
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#define TEGRA234_SID_HC_VM6 0x43U
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#define TEGRA234_SID_HC_VM7 0x44U
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/* SE data buffers */
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#define TEGRA234_SID_SE_VM0 0x45U
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#define TEGRA234_SID_SE_VM1 0x46U
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#define TEGRA234_SID_SE_VM2 0x47U
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#define TEGRA234_SID_ISPFALC 0x48U
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#define TEGRA234_SID_NISO1_SMMU_TEST 0x49U
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#endif /* _DT_BINDINGS_MEMORY_TEGRA234234_SMMU_STREAMID_H */
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