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cc5bcef3f6
Add the upstream host1x driver with the 'Host1x/Tegra UAPI' series [0] applied. This driver will be built as an external module for use with the NVGPU driver on upstream Linux kernels. The following modifications have been made to the series posted upstream 1. Update the Makefile to always build the driver as a module 2. Remove the tests to see if CONFIG_DRM_TEGRA_STAGING is enabled 3. Rename the include/linux/host1x.h to include/linux/host1x-next.h to avoid conflicts with upstream headers when building as an external module. 4. Rename the include/uapi/linux/host1x.h to include/uapi/linux/host1x-next.h to avoid conflicts with upstream headers when building as an external module. 5. Rename the module that is built to be host1x-next.ko instead of host1x.ko to avoid any depmod conflicts with the upstream driver. [0] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=215770 Bug 3156385 Change-Id: Ic60299546809097dd0e4a9a7157bce1491d9f794 Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2435801 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Tegra host1x Register Offsets for Tegra210
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*
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* Copyright (c) 2015 NVIDIA Corporation.
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*/
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#ifndef __HOST1X_HOST1X05_HARDWARE_H
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#define __HOST1X_HOST1X05_HARDWARE_H
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include "hw_host1x05_channel.h"
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#include "hw_host1x05_sync.h"
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#include "hw_host1x05_uclass.h"
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static inline u32 host1x_class_host_wait_syncpt(
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unsigned indx, unsigned threshold)
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{
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return host1x_uclass_wait_syncpt_indx_f(indx)
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| host1x_uclass_wait_syncpt_thresh_f(threshold);
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}
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static inline u32 host1x_class_host_load_syncpt_base(
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unsigned indx, unsigned threshold)
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{
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return host1x_uclass_load_syncpt_base_base_indx_f(indx)
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| host1x_uclass_load_syncpt_base_value_f(threshold);
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}
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static inline u32 host1x_class_host_wait_syncpt_base(
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unsigned indx, unsigned base_indx, unsigned offset)
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{
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return host1x_uclass_wait_syncpt_base_indx_f(indx)
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| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
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| host1x_uclass_wait_syncpt_base_offset_f(offset);
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}
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static inline u32 host1x_class_host_incr_syncpt_base(
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unsigned base_indx, unsigned offset)
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{
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return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
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| host1x_uclass_incr_syncpt_base_offset_f(offset);
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}
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static inline u32 host1x_class_host_incr_syncpt(
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unsigned cond, unsigned indx)
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{
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return host1x_uclass_incr_syncpt_cond_f(cond)
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| host1x_uclass_incr_syncpt_indx_f(indx);
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}
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static inline u32 host1x_class_host_indoff_reg_write(
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unsigned mod_id, unsigned offset, bool auto_inc)
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{
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u32 v = host1x_uclass_indoff_indbe_f(0xf)
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| host1x_uclass_indoff_indmodid_f(mod_id)
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| host1x_uclass_indoff_indroffset_f(offset);
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if (auto_inc)
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v |= host1x_uclass_indoff_autoinc_f(1);
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return v;
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}
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static inline u32 host1x_class_host_indoff_reg_read(
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unsigned mod_id, unsigned offset, bool auto_inc)
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{
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u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
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| host1x_uclass_indoff_indroffset_f(offset)
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| host1x_uclass_indoff_rwn_read_v();
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if (auto_inc)
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v |= host1x_uclass_indoff_autoinc_f(1);
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return v;
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}
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/* cdma opcodes */
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static inline u32 host1x_opcode_setclass(
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unsigned class_id, unsigned offset, unsigned mask)
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{
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return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
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}
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static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
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{
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return (1 << 28) | (offset << 16) | count;
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}
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static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
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{
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return (2 << 28) | (offset << 16) | count;
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}
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static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
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{
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return (3 << 28) | (offset << 16) | mask;
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}
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static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
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{
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return (4 << 28) | (offset << 16) | value;
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}
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static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
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{
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return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
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host1x_class_host_incr_syncpt(cond, indx));
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}
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static inline u32 host1x_opcode_restart(unsigned address)
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{
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return (5 << 28) | (address >> 4);
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}
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static inline u32 host1x_opcode_gather(unsigned count)
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{
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return (6 << 28) | count;
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}
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static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | count;
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}
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static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
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}
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#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
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#endif
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