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87f4a51862
Add DMA test function driver from Nvidia repro Bug 3583632 Change-Id: I603d16f74cba2b4752ab31af59b12e7c784f042e Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2736247 Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
187 lines
4.9 KiB
C
187 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PCIe DMA test framework for Tegra PCIe
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*
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* Copyright (C) 2021-2022 NVIDIA Corporation. All rights reserved.
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*/
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#ifndef PCIE_DMA_H
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#define PCIE_DMA_H
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/* Update DMA_DD_BUF_SIZE and DMA_LL_BUF_SIZE when changing BAR0_SIZE */
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#define BAR0_SIZE SZ_256M
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/* Header includes RP/EP DMA addresses, EP MSI, LL, etc. */
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#define BAR0_HEADER_OFFSET 0x0
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#define BAR0_HEADER_SIZE SZ_1M
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#define DMA_LL_OFFSET SZ_4K
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#define DMA_LL_SIZE SZ_4K /* 4K size of LL serve 170 desc */
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#define DMA_LL_WR_OFFSET(i) (DMA_LL_OFFSET + ((i) * DMA_LL_SIZE))
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#define DMA_LL_RD_OFFSET(i) (DMA_LL_WR_OFFSET(4) + ((i) * DMA_LL_SIZE))
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#define DMA_LL_MIN_SIZE 1
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#define DMA_LL_DEFAULT_SIZE 8
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#define DMA_ASYNC_LL_SIZE 160
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#define BAR0_MSI_OFFSET SZ_64K
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/* DMA'able memory range */
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#define BAR0_DMA_BUF_OFFSET SZ_1M
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#define BAR0_DMA_BUF_SIZE (BAR0_SIZE - SZ_1M)
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#define DMA_DD_BUF_SIZE SZ_32M
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#define DMA_LL_BUF_SIZE SZ_4M
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/* Each DMA LL channel gets DMA_DD_BUF_SIZE and each desc DMA_LL_BUF_SIZE */
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#define DMA_LL_WR_BUF(i) (BAR0_DMA_BUF_OFFSET + (i) * DMA_DD_BUF_SIZE)
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#define DMA_LL_RD_BUF(i) (DMA_LL_WR_BUF(4) + (i) * DMA_DD_BUF_SIZE)
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#define DEFAULT_STRESS_COUNT 10
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#define MAX_DMA_ELE_SIZE SZ_16M
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/* DMA base offset starts at 0x20000 from ATU_DMA base */
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#define DMA_OFFSET 0x20000
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#define DMA_RD_CHNL_NUM 2
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#define DMA_RD_CHNL_MASK 0x3
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#define DMA_WR_CHNL_NUM 4
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#define DMA_WR_CHNL_MASK 0xf
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/* DMA common registers */
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#define DMA_WRITE_ENGINE_EN_OFF 0xC
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#define WRITE_ENABLE BIT(0)
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#define WRITE_DISABLE 0x0
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#define DMA_WRITE_DOORBELL_OFF 0x10
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#define DMA_WRITE_DOORBELL_OFF_WR_STOP BIT(31)
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#define DMA_READ_ENGINE_EN_OFF 0x2C
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#define READ_ENABLE BIT(0)
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#define READ_DISABLE 0x0
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#define DMA_READ_DOORBELL_OFF 0x30
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#define DMA_READ_DOORBELL_OFF_RD_STOP BIT(31)
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#define DMA_WRITE_INT_STATUS_OFF 0x4C
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#define DMA_WRITE_INT_MASK_OFF 0x54
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#define DMA_WRITE_INT_CLEAR_OFF 0x58
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#define DMA_WRITE_INT_DONE_MASK 0xF
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#define DMA_WRITE_INT_ABORT_MASK 0xF0000
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#define DMA_WRITE_ERR_STATUS_OFF 0x5C
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#define DMA_WRITE_DONE_IMWR_LOW_OFF 0x60
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#define DMA_WRITE_DONE_IMWR_HIGH_OFF 0x64
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#define DMA_WRITE_ABORT_IMWR_LOW_OFF 0x68
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#define DMA_WRITE_ABORT_IMWR_HIGH_OFF 0x6C
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#define DMA_WRITE_IMWR_DATA_OFF_BASE 0x70
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#define DMA_READ_INT_STATUS_OFF 0xA0
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#define DMA_READ_INT_MASK_OFF 0xA8
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#define DMA_READ_INT_CLEAR_OFF 0xAC
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#define DMA_READ_INT_DONE_MASK 0xF
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#define DMA_READ_INT_ABORT_MASK 0xF0000
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#define DMA_READ_DONE_IMWR_LOW_OFF 0xCC
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#define DMA_READ_DONE_IMWR_HIGH_OFF 0xD0
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#define DMA_READ_ABORT_IMWR_LOW_OFF 0xD4
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#define DMA_READ_ABORT_IMWR_HIGH_OFF 0xD8
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#define DMA_READ_IMWR_DATA_OFF_BASE 0xDC
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/* DMA channel specific registers */
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#define DMA_CH_CONTROL1_OFF_WRCH 0x0
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#define DMA_CH_CONTROL1_OFF_WRCH_LLE BIT(9)
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#define DMA_CH_CONTROL1_OFF_WRCH_CCS BIT(8)
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#define DMA_CH_CONTROL1_OFF_WRCH_RIE BIT(4)
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#define DMA_CH_CONTROL1_OFF_WRCH_LIE BIT(3)
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#define DMA_CH_CONTROL1_OFF_WRCH_LLP BIT(2)
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#define DMA_TRANSFER_SIZE_OFF_WRCH 0x8
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#define DMA_SAR_LOW_OFF_WRCH 0xC
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#define DMA_SAR_HIGH_OFF_WRCH 0x10
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#define DMA_DAR_LOW_OFF_WRCH 0x14
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#define DMA_DAR_HIGH_OFF_WRCH 0x18
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#define DMA_LLP_LOW_OFF_WRCH 0x1C
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#define DMA_LLP_HIGH_OFF_WRCH 0x20
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#define DMA_CH_CONTROL1_OFF_RDCH 0x100
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#define DMA_CH_CONTROL1_OFF_RDCH_LLE BIT(9)
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#define DMA_CH_CONTROL1_OFF_RDCH_CCS BIT(8)
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#define DMA_CH_CONTROL1_OFF_RDCH_RIE BIT(4)
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#define DMA_CH_CONTROL1_OFF_RDCH_LIE BIT(3)
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#define DMA_CH_CONTROL1_OFF_RDCH_LLP BIT(2)
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#define DMA_TRANSFER_SIZE_OFF_RDCH 0x108
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#define DMA_SAR_LOW_OFF_RDCH 0x10C
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#define DMA_SAR_HIGH_OFF_RDCH 0x110
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#define DMA_DAR_LOW_OFF_RDCH 0x114
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#define DMA_DAR_HIGH_OFF_RDCH 0x118
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#define DMA_LLP_LOW_OFF_RDCH 0x11C
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#define DMA_LLP_HIGH_OFF_RDCH 0x120
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struct sanity_data {
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u32 size;
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u32 crc;
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};
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/* First 1MB of BAR0 is reserved for control data */
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struct pcie_epf_bar0 {
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/* RP system memory allocated for EP DMA operations */
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u64 rp_phy_addr;
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/* EP system memory allocated as BAR */
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u64 ep_phy_addr;
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/* MSI data for RP -> EP interrupts */
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u32 msi_data[DMA_WR_CHNL_NUM + DMA_RD_CHNL_NUM];
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struct sanity_data wr_data[DMA_WR_CHNL_NUM];
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struct sanity_data rd_data[DMA_RD_CHNL_NUM];
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};
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struct dma_ll_ctrl {
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u32 cb:1;
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u32 tcb:1;
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u32 llp:1;
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u32 lie:1;
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u32 rie:1;
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};
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struct dma_ll {
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volatile struct dma_ll_ctrl ele;
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u32 size;
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u32 src_low;
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u32 src_high;
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u32 dst_low;
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u32 dst_high;
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};
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static inline void dma_common_wr16(void __iomem *p, u32 val, u32 offset)
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{
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writew(val, offset + p);
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}
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static inline u16 dma_common_rd16(void __iomem *p, u32 offset)
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{
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return readw(offset + p);
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}
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static inline void dma_common_wr(void __iomem *p, u32 val, u32 offset)
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{
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writel(val, offset + p);
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}
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static inline u32 dma_common_rd(void __iomem *p, u32 offset)
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{
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return readl(offset + p);
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}
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static inline void dma_channel_wr(void __iomem *p, u8 channel, u32 val,
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u32 offset)
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{
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writel(val, (0x200 * (channel + 1)) + offset + p);
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}
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static inline u32 dma_channel_rd(void __iomem *p, u8 channel, u32 offset)
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{
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return readl((0x200 * (channel + 1)) + offset + p);
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}
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#endif
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