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e9881b2cee
When PCIe link is disabled or secondary bus reset is done by RP, EP LTSSM state goes to link disable or hot reset respectively. Update the LTSSM state check accordingly to support link disable and secondary bus reset. XTL_EP_PRI_BAR_CONFIG and XTL_EP_PRI_RESIZE_BAR1 are part of hot reset domain, when link is going through hot reset, these registers are not accessible. So, remove these register programming in tegra264_pcie_ep_clear_bar(). After hot reset these registers come back with reset values. Bug 4712053 Change-Id: Ieaf37ed9fed6722db8a16027947121b1cfd1ef4c Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3163927 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>