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ee8192fe65
1. Remove replicate bit and add fifo_size_downshift bit in cif 2. Update mask value for dma_fifo_size, dma_fifo_start_addr and dma_fifo_threshold in admaif driver 3. Update the copyright 4. Add run time check function to detect FPGA Bug 1582514 Bug 1582510 Change-Id: I40a8172ebc3713ead4cb5764f291f04d548c7a75 Signed-off-by: Junghyun Kim <juskim@nvidia.com> Reviewed-on: http://git-master/r/751602 Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com> Tested-by: Arun Shamanna Lakshmi <aruns@nvidia.com>