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7e861f8a9e
* Updates misc/mods from Perforce * Adds support for updated ATF RIST SMCs Change-Id: I84975bb5dee6775ae415167d78799ecd38cb888f Signed-off-by: Ian Grissom <igrissom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3146201 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Dipen Patel <dipenp@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved. */
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#include "mods_internal.h"
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#include <linux/arm-smccc.h>
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#define SMCCC_VERSION 0x80000000
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#define TEGRA_SIP_RIST_SETUP 0xC200FF08
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#define TEGRA_SIP_RIST_STATUS 0xC200FF04
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#define TEGRA_SIP_RIST_STATUS_v2 0xC200FF09
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/*
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* MODS_ESC_OIST_STATUS is used to make SMC calls to the ATF driver for
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* OIST/RIST.
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*
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* The 'smc_func_id' is used to controal the SMC function ID. Potential SMC IDs
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* include SMCCC_VERSION, TEGRA_SIP_RIST_STATUS, TEGRA_SIP_RIST_STATUS_v2,
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* and TEGRA_SIP_RIST_SETUP.
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*
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* The 'aX' fields are used to populate the input parameters to the various SMC
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* calls. The remaining fields ('smc_status', 'smc_retval', ist_status',
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* 'rist_setup_done') are used to relay return information back to the caller
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*
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* Input parameters --
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* SMCCC_VERSION:
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* a1 - unused, but a default value of 0 is passed
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* TEGRA_SIP_RIST_STATUS:
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* a1 - logical core ID to retrieve status for
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* a2 - unused but expected to pass value of 1
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* TEGRA_SIP_RIST_STATUS_v2:
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* a1 - physical core ID to retrieve status for
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* TEGRA_SIP_RIST_SETUP:
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* a1 - test vector data physical address
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* a2 - test vector data size
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* a3 - event timer buffer physical address
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* a4 - 'pll_sel' (bit 0) feature enable/disable
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*/
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int esc_mods_oist_status(struct mods_client *client,
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struct MODS_TEGRA_OIST_STATUS *p)
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{
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int ret = 0;
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struct arm_smccc_res res = { 0 };
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LOG_ENT();
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switch (p->smc_func_id) {
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case SMCCC_VERSION:
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// For SMC version, We are only reading res.a0 value, not a1,a2,a3
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arm_smccc_1_1_smc(p->smc_func_id, res.a0, &res);
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p->smc_status = res.a0;
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break;
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case TEGRA_SIP_RIST_STATUS:
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// a1 - logical core ID
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// a2 - unused on some implementations, but passed to be compatible
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arm_smccc_1_1_smc(p->smc_func_id, p->a1, p->a2, &res);
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p->smc_retval = res.a0;
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p->smc_status = res.a1;
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p->ist_status = res.a2;
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break;
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case TEGRA_SIP_RIST_STATUS_v2:
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// a1 - physical core ID
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// a2 - unused on some implementations, but passed to be compatible
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arm_smccc_1_1_smc(p->smc_func_id, p->a1, p->a2, &res);
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p->smc_retval = res.a0;
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p->smc_status = res.a1;
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p->ist_status = res.a2;
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break;
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case TEGRA_SIP_RIST_SETUP:
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// a1 - tvt_addr
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// a2 - tvt_size
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// a3 - evt_buff
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// a4 - pll_sel (bit 0)
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arm_smccc_1_1_smc(p->smc_func_id, p->a1, p->a2, p->a3, p->a4, &res);
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p->smc_retval = res.a0;
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p->rist_setup_done = res.a1;
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break;
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default:
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cl_error("invalid smc_func_id 0x%llx\n",
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(unsigned long long)p->smc_func_id);
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LOG_EXT();
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ret = -EINVAL;
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}
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LOG_EXT();
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return ret;
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}
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