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RAS are three aspects of the dependability of a system: Reliability: continuity of correct service Availability: readiness for correct service Serviceability: ability to undergo modifications and repairs ARMv8.2 provides RAS extensions to achieve the above features in a system. arm64_ras driver allows you to handle Correctable errors using per core Fault Handling Interrupt (or FHI). Un-correactable errors are handled by raising SError exception to kernel or Trusted Firmware(EL3) on CCLEX. The driver provides an API for CPU specific RAS drivers to register callbacks in case of FHI. When FHI occurs, the FHI ISR goes through the list of registered callbacks and executes them. Similarly, the driver allows registering SError callbacks for Un-correctable errors within Core, Core-Cluster & CCPLEX. When SError is reported, then those callbacks are scanned to find and report error in a Core, Cluster or CCPLEX Bug 3625675 Change-Id: I6dba7178fa7bbcf55bfa083be1b077874f4865c9 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2705396 GVS: Gerrit_Virtual_Submit
86 lines
2.5 KiB
C
86 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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#ifndef _LINUX_ARM64_RAS_H__
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#define _LINUX_ARM64_RAS_H__
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struct ras_error {
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char *name;
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u16 error_code;
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};
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struct error_record {
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struct list_head node;
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char *name;
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u64 errx;
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u8 processed;
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u64 err_ctlr;
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struct ras_error *errors;
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};
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#define RAS_BIT(_bit_) (1ULL << (_bit_))
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#define RAS_MASK(_msb_, _lsb_) \
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((RAS_BIT(_msb_+1) - 1ULL) & ~(RAS_BIT(_lsb_) - 1ULL))
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#define RAS_EXTRACT(_x_, _msb_, _lsb_) \
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((_x_ & RAS_MASK(_msb_, _lsb_)) >> _lsb_)
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#define RAS_CTL_CFI RAS_BIT(8)
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#define RAS_CTL_UE RAS_BIT(4)
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#define RAS_CTL_ED RAS_BIT(0)
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#define ERRi_STATUS_UET ((RAS_BIT(20)) | (RAS_BIT(21)))
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#define ERRi_STATUS_CE ((RAS_BIT(24)) | (RAS_BIT(25)))
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#define ERRi_STATUS_MV RAS_BIT(26)
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#define ERRi_STATUS_OF RAS_BIT(27)
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#define ERRi_STATUS_UE RAS_BIT(29)
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#define ERRi_STATUS_VALID RAS_BIT(30)
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#define ERRi_STATUS_AV RAS_BIT(31)
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#define ERRi_PFGCTL_CDNEN RAS_BIT(31)
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#define ERRi_PFGCTL_R RAS_BIT(30)
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#define ERRi_PFGCTL_CE RAS_BIT(6)
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#define ERRi_PFGCTL_UC RAS_BIT(1)
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#define ERRi_PFGCDN_CDN_1 0x1
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#define get_error_status_ce(_x_) RAS_EXTRACT(_x_, 25, 24)
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#define get_error_status_ierr(_x_) RAS_EXTRACT(_x_, 15, 8)
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#define get_error_status_serr(_x_) RAS_EXTRACT(_x_, 7, 0)
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struct ras_fhi_callback {
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struct list_head node;
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void (*fn)(void);
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};
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/* Macros for reading ID_PFR0 - RAS Version field */
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#define PFR0_RAS_SHIFT 28
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#define PFR0_RAS_MASK (0xf << PFR0_RAS_SHIFT)
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#define PFR0_RAS(pfr0) \
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(((pfr0) & PFR0_RAS_MASK) >> PFR0_RAS_SHIFT)
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#define PFR0_RAS_VERSION_1 0x1
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/* RAS functions needed by ras_carmel driver */
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int is_ras_ready(void);
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int is_this_ras_cpu(void);
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int is_ras_cpu(int cpu);
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u64 ras_read_error_status(void);
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u64 ras_read_errselr(void);
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u64 ras_read_pfg_control(void);
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u64 ras_read_pfg_cdn(void);
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u64 ras_read_error_control(void);
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u64 ras_read_feature_reg(void);
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void ras_write_error_control(u64 err_ctl);
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void ras_write_error_status(u64 status);
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void ras_write_error_addr(u64 addr);
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void ras_write_error_misc0(u64 misc0);
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void ras_write_error_misc1(u64 misc1);
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void ras_write_error_statustrigger(u64 status);
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void ras_write_pfg_control(u64 pfg_ctl);
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void ras_write_pfg_cdn(u64 pfg_cdn);
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void ras_write_errselr(u64 errx);
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void print_error_record(struct error_record *record, u64 status, int errselr);
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int register_fhi_callback(struct ras_fhi_callback *callback, void *cookie);
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void unregister_fhi_callback(struct ras_fhi_callback *callback);
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#endif // _LINUX_ARM64_RAS_H__
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