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f6ea9a46d2
we can't use just one edge register for active and inactive edge, with 1ns tsc clock width and only 28 bits for edge offset register, we need to split the active tsc ticks between 2 edge registers. Jira CAMERASW-30089 Change-Id: I290b2c131ead9e89832445b0a4ee35e9f48e27c5 Signed-off-by: Mohit Ingale <mohiti@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3270199 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Frank Chen <frankc@nvidia.com> Reviewed-by: Ian Kaszubski <ikaszubski@nvidia.com> Reviewed-by: Jagadeesh Kinni <jkinni@nvidia.com> Reviewed-by: Shiva Dubey <sdubey@nvidia.com>