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e69d77ec71
Add command specifications for RCE I2C HSP protocol. Jira CAMERASW-1404 Change-Id: I17cbe234371140934b04e3a9683aa1cbc7d5ef91 Signed-off-by: Mika Liljeberg <mliljeberg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/tegra/camera/firmware-api/+/2701487 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2988962 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2988975 GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Reviewed-by: Matti Ryttylainen <mryttylainen@nvidia.com> Reviewed-by: Viktor Horsmanheimo <viktorh@nvidia.com>
235 lines
6.9 KiB
C
235 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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/**
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* @file camrtc-commands.h
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*
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* @brief Commands used with "nvidia,tegra-camrtc-hsp-vm" & "nvidia,tegra-hsp-mailbox"
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* protocol
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*/
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#ifndef INCLUDE_CAMRTC_COMMANDS_H
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#define INCLUDE_CAMRTC_COMMANDS_H
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#include "camrtc-common.h"
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/**
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* @defgroup HspVmMsgs Definitions for "nvidia,tegra-camrtc-hsp-vm" protocol
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* @{
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*/
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#define CAMRTC_HSP_MSG(_id, _param) ( \
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((uint32_t)(_id) << MK_U32(24)) | \
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((uint32_t)(_param) & MK_U32(0xffffff)))
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#define CAMRTC_HSP_MSG_ID(_msg) \
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(((_msg) >> MK_U32(24)) & MK_U32(0x7f))
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#define CAMRTC_HSP_MSG_PARAM(_msg) \
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((uint32_t)(_msg) & MK_U32(0xffffff))
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/**
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* The IRQ message is sent when no other HSP-VM protocol message is being sent
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* (i.e. the messages for higher level protocols implementing HSP such as IVC
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* channel protocol) and the sender has updated its shared semaphore bits.
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*/
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#define CAMRTC_HSP_IRQ MK_U32(0x00)
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/**
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* Configure I2C controller. This will activate the given
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* I2C controller and configure the base address of a shared memory
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* buffer for subsequent I2C transfers. Buffer must be page aligned.
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*
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* param[23:20] = I2C bus ID
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* param[19:0] = Bits [31:12] of shared memory buffer bus address
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*/
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#define CAMRTC_HSP_I2C_INIT MK_U32(0x10)
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/**
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* Configure I2C device address. This will set the slave device
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* for subsequent I2C transfers.
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*
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* param[23:20] = I2C bus ID
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* param[10:10] = 10-bit address flag
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* param[9:0] = device address
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*/
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#define CAMRTC_HSP_I2C_DEVICE MK_U32(0x11)
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/**
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* Perform I2C transfer. The same shared memory buffer will be used
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* for send and receive. Either byte count may be set to zero.
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*
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* param[23:12] = recv byte count
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* param[11:0] = send byte count
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*/
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#define CAMRTC_HSP_I2C_XFER MK_U32(0x12)
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/**
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* The HELLO messages are exchanged at the beginning of VM and RCE FW session.
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* The HELLO message exchange ensures there are no unprocessed messages
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* in transit within VM or RCE FW.
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*/
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#define CAMRTC_HSP_HELLO MK_U32(0x40)
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/**
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* VM session close in indicated using BYE message,
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* RCE FW reclaims the resources assigned to given VM.
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* It must be sent before the Camera VM shuts down self.
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*/
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#define CAMRTC_HSP_BYE MK_U32(0x41)
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/**
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* The RESUME message is sent when VM wants to activate the RCE FW
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* and access the camera hardware through it.
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*/
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#define CAMRTC_HSP_RESUME MK_U32(0x42)
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/**
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* Power off camera HW, switch to idle state. VM initiates it during runtime suspend or SC7.
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*/
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#define CAMRTC_HSP_SUSPEND MK_U32(0x43)
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/**
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* Used to set up a shared memory area (such as IVC channels, trace buffer etc)
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* between Camera VM and RCE FW.
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*/
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#define CAMRTC_HSP_CH_SETUP MK_U32(0x44)
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/**
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* The Camera VM can use the PING message to check aliveness of RCE FW and the HSP protocol.
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*/
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#define CAMRTC_HSP_PING MK_U32(0x45)
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/**
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* SHA1 hash code for RCE FW binary.
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*/
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#define CAMRTC_HSP_FW_HASH MK_U32(0x46)
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/**
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* The VM includes its protocol version as a parameter to PROTOCOL message.
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* FW responds with its protocol version, or RTCPU_FW_INVALID_VERSION
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* if the VM protocol is not supported.
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*/
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#define CAMRTC_HSP_PROTOCOL MK_U32(0x47)
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#define CAMRTC_HSP_RESERVED_5E MK_U32(0x5E) /* bug 200395605 */
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#define CAMRTC_HSP_UNKNOWN MK_U32(0x7F)
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/** Shared semaphore bits (FW->VM) */
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#define CAMRTC_HSP_SS_FW_MASK MK_U32(0xFFFF)
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#define CAMRTC_HSP_SS_FW_SHIFT MK_U32(0)
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/** Shared semaphore bits (VM->FW) */
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#define CAMRTC_HSP_SS_VM_MASK MK_U32(0x7FFF0000)
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#define CAMRTC_HSP_SS_VM_SHIFT MK_U32(16)
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/** Bits used by IVC channels */
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#define CAMRTC_HSP_SS_IVC_MASK MK_U32(0xFF)
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/** @} */
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/**
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* @defgroup HspMailboxMsgs Definitions for "nvidia,tegra-hsp-mailbox" protocol
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* @{
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*/
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#define RTCPU_COMMAND(id, value) \
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(((RTCPU_CMD_ ## id) << MK_U32(24)) | ((uint32_t)value))
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#define RTCPU_GET_COMMAND_ID(value) \
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((((uint32_t)value) >> MK_U32(24)) & MK_U32(0x7f))
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#define RTCPU_GET_COMMAND_VALUE(value) \
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(((uint32_t)value) & MK_U32(0xffffff))
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/**
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* RCE FW waits until VM client initiates boot sync with INIT HSP command.
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*/
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#define RTCPU_CMD_INIT MK_U32(0)
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/**
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* VM client sends host version and expects RCE FW to respond back with
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* current FW version, as part of boot sync.
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*/
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#define RTCPU_CMD_FW_VERSION MK_U32(1)
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#define RTCPU_CMD_RESERVED_02 MK_U32(2)
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#define RTCPU_CMD_RESERVED_03 MK_U32(3)
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/**
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* Release RCE FW resources assigned to given VM client, during runtime suspend or SC7.
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*/
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#define RTCPU_CMD_PM_SUSPEND MK_U32(4)
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#define RTCPU_CMD_RESERVED_05 MK_U32(5)
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/**
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* Used to set up a shared memory area (such as IVC channels, trace buffer etc)
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* between Camera VM and RCE FW.
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*/
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#define RTCPU_CMD_CH_SETUP MK_U32(6)
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/**
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* Configure I2C controller. This will activate the given
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* I2C controller and configure the base address of a shared memory
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* buffer for subsequent I2C transfers. Buffer must be page aligned.
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*
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* param[23:20] = I2C bus ID
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* param[19:0] = Bits [31:12] of shared memory buffer bus address
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*/
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#define RTCPU_CMD_I2C_INIT MK_U32(0x10)
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/**
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* Configure I2C device address. This will set the slave device
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* for subsequent I2C transfers.
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*
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* param[23:20] = I2C bus ID
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* param[10:10] = 10-bit address flag
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* param[9:0] = device address
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*/
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#define RTCPU_CMD_I2C_DEVICE MK_U32(0x11)
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/**
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* Perform I2C transfer. The same shared memory buffer will be used
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* for send and receive. Either byte count may be set to zero.
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*
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* param[23:12] = recv byte count
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* param[11:0] = send byte count
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*/
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#define RTCPU_CMD_I2C_XFER MK_U32(0x12)
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#define RTCPU_CMD_RESERVED_5E MK_U32(0x5E) /* bug 200395605 */
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#define RTCPU_CMD_RESERVED_7D MK_U32(0x7d)
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#define RTCPU_CMD_RESERVED_7E MK_U32(0x7e)
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#define RTCPU_CMD_ERROR MK_U32(0x7f)
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#define RTCPU_FW_DB_VERSION MK_U32(0)
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#define RTCPU_FW_VERSION MK_U32(1)
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#define RTCPU_FW_SM2_VERSION MK_U32(2)
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#define RTCPU_FW_SM3_VERSION MK_U32(3)
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/** SM4 firmware can restore itself after suspend */
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#define RTCPU_FW_SM4_VERSION MK_U32(4)
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/** SM5 firmware supports IVC synchronization */
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#define RTCPU_FW_SM5_VERSION MK_U32(5)
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/** SM5 driver supports IVC synchronization */
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#define RTCPU_DRIVER_SM5_VERSION MK_U32(5)
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/** SM6 firmware/driver supports camrtc-hsp-vm protocol */
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#define RTCPU_FW_SM6_VERSION MK_U32(6)
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#define RTCPU_DRIVER_SM6_VERSION MK_U32(6)
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#define RTCPU_IVC_SANS_TRACE MK_U32(1)
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#define RTCPU_IVC_WITH_TRACE MK_U32(2)
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#define RTCPU_FW_HASH_SIZE MK_U32(20)
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#define RTCPU_FW_HASH_ERROR MK_U32(0xFFFFFF)
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#define RTCPU_PM_SUSPEND_SUCCESS MK_U32(0x100)
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#define RTCPU_PM_SUSPEND_FAILURE MK_U32(0x001)
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#define RTCPU_FW_CURRENT_VERSION RTCPU_FW_SM6_VERSION
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#define RTCPU_FW_INVALID_VERSION MK_U32(0xFFFFFF)
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#define RTCPU_RESUME_ERROR MK_U32(0xFFFFFF)
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/** @} */
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/**
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* @defgroup I2C HSP protocol responses
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* @{
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*/
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#define RTCPU_I2C_DONE MK_U32(1)
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#define RTCPU_I2C_ERROR MK_U32(2)
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#define RTCPU_I2C_NACK MK_U32(3)
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#define RTCPU_I2C_ARBL MK_U32(4)
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/** @} */
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#endif /* INCLUDE_CAMRTC_COMMANDS_H */
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