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gpu: nvgpu: move cur_gr_instance tracking to MIG infra

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Move cur_gr_instance from struct gk20a to struct nvgpu_mig since this
tracking is really MIG specific.

Jira NVGPU-5648

Change-Id: I27b124925c2291e352ef9456c7189da0bc447a42
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2406389
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2020-08-31 11:35:16 +05:30
committed by Alex Waterman
parent a6d7b48665
commit 002edb782a
4 changed files with 13 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -614,7 +614,7 @@ static int gr_reset_engine(struct gk20a *g)
if (g->ops.gr.init.reset_gpcs != NULL) {
const struct nvgpu_device *dev =
nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS,
nvgpu_gr_get_syspipe_id(g, g->cur_gr_instance));
nvgpu_gr_get_syspipe_id(g, g->mig.cur_gr_instance));
g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
@@ -841,7 +841,7 @@ int nvgpu_gr_alloc(struct gk20a *g)
return -ENOMEM;
}
g->cur_gr_instance = 0U; /* default */
g->mig.cur_gr_instance = 0U; /* default */
for (i = 0U; i < g->num_gr_instances; i++) {
gr = &g->gr[i];

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -335,7 +335,6 @@ struct gk20a {
struct nvgpu_gr *gr;
u32 num_gr_instances;
u32 cur_gr_instance;
struct nvgpu_fbp *fbp;
#ifdef CONFIG_NVGPU_SIM

10
drivers/gpu/nvgpu/include/nvgpu/gr/gr_instances.h
View File

@@ -35,7 +35,7 @@
while (gr_instance_id < g->num_gr_instances) { \
u32 gr_syspipe_id = nvgpu_gr_get_syspipe_id(g, gr_instance_id); \
nvgpu_grmgr_config_gr_remap_window(g, gr_syspipe_id, true); \
g->cur_gr_instance = gr_instance_id; \
g->mig.cur_gr_instance = gr_instance_id; \
(func); \
nvgpu_grmgr_config_gr_remap_window(g, gr_syspipe_id, false); \
} \
@@ -56,7 +56,7 @@
while (gr_instance_id < g->num_gr_instances) { \
u32 gr_syspipe_id = nvgpu_gr_get_syspipe_id(g, gr_instance_id); \
nvgpu_grmgr_config_gr_remap_window(g, gr_syspipe_id, true); \
g->cur_gr_instance = gr_instance_id; \
g->mig.cur_gr_instance = gr_instance_id; \
err = (func); \
if (err != 0) { \
break; \
@@ -77,7 +77,7 @@
({ \
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
nvgpu_grmgr_config_gr_remap_window(g, NVGPU_MIG_INVALID_GR_SYSPIPE_ID, false); \
g->cur_gr_instance = 0; \
g->mig.cur_gr_instance = 0; \
(func); \
nvgpu_grmgr_config_gr_remap_window(g, NVGPU_MIG_INVALID_GR_SYSPIPE_ID, true); \
} else { \
@@ -94,7 +94,7 @@
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
u32 gr_syspipe_id = nvgpu_gr_get_syspipe_id(g, gr_instance_id); \
nvgpu_grmgr_config_gr_remap_window(g, gr_syspipe_id, true); \
g->cur_gr_instance = gr_instance_id; \
g->mig.cur_gr_instance = gr_instance_id; \
(func); \
nvgpu_grmgr_config_gr_remap_window(g, gr_syspipe_id, false); \
} else { \
@@ -112,7 +112,7 @@
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { \
u32 gr_syspipe_id = nvgpu_gr_get_syspipe_id(g, gr_instance_id); \
nvgpu_grmgr_config_gr_remap_window(g, gr_syspipe_id, true); \
g->cur_gr_instance = gr_instance_id; \
g->mig.cur_gr_instance = gr_instance_id; \
err = (func); \
nvgpu_grmgr_config_gr_remap_window(g, gr_syspipe_id, false); \
} else { \

6
drivers/gpu/nvgpu/include/nvgpu/mig.h
View File

@@ -196,6 +196,12 @@ struct nvgpu_mig {
* It is valid if num_gr_sys_pipes_enabled > 1.
*/
u32 current_gr_syspipe_id;
/*
* Current GR instance being programmed.
* Defaults to zero for non-MIG cases. Respective GR instance id in
* case MIG support is enabled.
*/
u32 cur_gr_instance;
/**
* GR syspipe acquire lock.
* It is valid lock if num_gr_sys_pipes_enabled > 1.