gpu: gp10b: add gfxp_wfi_timeout sysfs node

Add a sysfs node to allow root user to set PRI_FE_GFXP_WFI_TIMEOUT, for gp10b
only, in units of sysclk cycles. Store the set value in a variable, and write
the set value to register after GPU is un-railgated.

NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT is engine_reset after Bug 1623341.

Change default value to be specified in cycles, rather than time.  This value
is almost the current value in cycles calculated each boot.

Bug 1932782

Change-Id: I0a4207e637cd1413a1be95abe2bcce3adccf76fa
Reviewed-on: https://git-master.nvidia.com/r/1540939
Signed-off-by: Jonathan McCaffrey <jmccaffrey@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1580999
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/linux/sysfs.c

@@ -954,6 +954,52 @@ static ssize_t pd_max_batches_read(struct device *dev,
 
 static DEVICE_ATTR(pd_max_batches, ROOTRW, pd_max_batches_read, pd_max_batches_store);
 
+static ssize_t gfxp_wfi_timeout_count_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct gr_gk20a *gr = &g->gr;
+	unsigned long val = 0;
+	int err = -1;
+
+	if (kstrtoul(buf, 10, &val) < 0)
+		return -EINVAL;
+
+	if (val >= 100*1000*1000) /* 100ms @ 1Ghz */
+		return -EINVAL;
+
+	gr->gfxp_wfi_timeout_count = val;
+
+	if (g->ops.gr.init_preemption_state && g->power_on) {
+		err = gk20a_busy(g);
+		if (err)
+			return err;
+
+		err = gr_gk20a_elpg_protected_call(g,
+			g->ops.gr.init_preemption_state(g));
+
+		gk20a_idle(g);
+
+		if (err)
+			return err;
+	}
+
+	return count;
+}
+
+static ssize_t gfxp_wfi_timeout_count_read(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct gr_gk20a *gr = &g->gr;
+	u32 val = gr->gfxp_wfi_timeout_count;
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", val);
+}
+
+static DEVICE_ATTR(gfxp_wfi_timeout_count, (S_IRWXU|S_IRGRP|S_IROTH),
+		gfxp_wfi_timeout_count_read, gfxp_wfi_timeout_count_store);
+
 
 void nvgpu_remove_sysfs(struct device *dev)
 {
@@ -989,6 +1035,7 @@ void nvgpu_remove_sysfs(struct device *dev)
 
 	device_remove_file(dev, &dev_attr_czf_bypass);
 	device_remove_file(dev, &dev_attr_pd_max_batches);
+	device_remove_file(dev, &dev_attr_gfxp_wfi_timeout_count);
 
 	if (strcmp(dev_name(dev), "gpu.0")) {
 		struct kobject *kobj = &dev->kobj;
@@ -1035,6 +1082,7 @@ int nvgpu_create_sysfs(struct device *dev)
 
 	error |= device_create_file(dev, &dev_attr_czf_bypass);
 	error |= device_create_file(dev, &dev_attr_pd_max_batches);
+	error |= device_create_file(dev, &dev_attr_gfxp_wfi_timeout_count);
 
 	if (strcmp(dev_name(dev), "gpu.0")) {
 		struct kobject *kobj = &dev->kobj;

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -78,6 +78,7 @@
 #define CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT 10
 #define FECS_ARB_CMD_TIMEOUT_MAX 40
 #define FECS_ARB_CMD_TIMEOUT_DEFAULT 2
+#define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000
 
 static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g);
 
@@ -4841,6 +4842,8 @@ static int gk20a_init_gr_setup_sw(struct gk20a *g)
 	if (g->ops.gr.init_czf_bypass)
 		g->ops.gr.init_czf_bypass(g);
 
+	gr->gfxp_wfi_timeout_count = GFXP_WFI_TIMEOUT_COUNT_DEFAULT;
+
 	nvgpu_mutex_init(&gr->ctx_mutex);
 	nvgpu_spinlock_init(&gr->ch_tlb_lock);
 

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -343,6 +343,7 @@ struct gr_gk20a {
 	u32 timeslice_mode;
 	u32 czf_bypass;
 	u32 pd_max_batches;
+	u32 gfxp_wfi_timeout_count;
 
 	struct gr_ctx_buffer_desc global_ctx_buffer[NR_GLOBAL_CTX_BUF];
 

drivers/gpu/nvgpu/gp10b/gr_gp10b.c

@@ -49,8 +49,6 @@
 #include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
 
-#define NVGPU_GFXP_WFI_TIMEOUT_US	100LL
-
 bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num)
 {
 	bool valid = false;
@@ -2336,11 +2334,8 @@ int gp10b_gr_fuse_override(struct gk20a *g)
 int gr_gp10b_init_preemption_state(struct gk20a *g)
 {
 	u32 debug_2;
-	u64 sysclk_rate;
-	u32 sysclk_cycles;
-
-	sysclk_rate = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPCCLK);
-	sysclk_cycles = (u32)((sysclk_rate * NVGPU_GFXP_WFI_TIMEOUT_US) / 1000000ULL);
+	struct gr_gk20a *gr = &g->gr;
+	u32 sysclk_cycles = gr->gfxp_wfi_timeout_count;
 	gk20a_writel(g, gr_fe_gfxp_wfi_timeout_r(),
 			gr_fe_gfxp_wfi_timeout_count_f(sysclk_cycles));