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gpu: nvgpu: fb: fix MISRA 10.3 violations

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This fixes a number of MISRA Rule 10.3 violations for assignment of
objects of different essential type or size in the common/fb unit.

JIRA NVGPU-2954

Change-Id: I02e4e9a9789f355497900da2113d8f0c5a102336
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075596
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-03-18 10:30:53 -04:00
committed by mobile promotions
parent f9c4d6b60b
commit 012c8f983f
4 changed files with 23 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/nvgpu/hal/fb/fb_gm20b.c
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@@ -27,6 +27,7 @@
#include <nvgpu/sizes.h>
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include "fb_gm20b.h"
@@ -42,30 +43,33 @@ void gm20b_fb_init_hw(struct gk20a *g)
{
u64 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8;
gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), addr);
nvgpu_assert(u64_hi32(addr) == 0U);
gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), U32(addr));
/* init mmu debug buffer */
addr = nvgpu_mem_get_addr(g, &g->mm.mmu_wr_mem);
addr >>= fb_mmu_debug_wr_addr_alignment_v();
nvgpu_assert(u64_hi32(addr) == 0U);
gk20a_writel(g, fb_mmu_debug_wr_r(),
nvgpu_aperture_mask(g, &g->mm.mmu_wr_mem,
fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
fb_mmu_debug_wr_aperture_sys_mem_coh_f(),
fb_mmu_debug_wr_aperture_vid_mem_f()) |
fb_mmu_debug_wr_vol_false_f() |
fb_mmu_debug_wr_addr_f(addr));
fb_mmu_debug_wr_addr_f(U32(addr)));
addr = nvgpu_mem_get_addr(g, &g->mm.mmu_rd_mem);
addr >>= fb_mmu_debug_rd_addr_alignment_v();
nvgpu_assert(u64_hi32(addr) == 0U);
gk20a_writel(g, fb_mmu_debug_rd_r(),
nvgpu_aperture_mask(g, &g->mm.mmu_rd_mem,
fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
fb_mmu_debug_wr_aperture_sys_mem_coh_f(),
fb_mmu_debug_rd_aperture_vid_mem_f()) |
fb_mmu_debug_rd_vol_false_f() |
fb_mmu_debug_rd_addr_f(addr));
fb_mmu_debug_rd_addr_f(U32(addr)));
}
int gm20b_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
@@ -198,7 +202,7 @@ u64 gm20b_fb_compression_page_size(struct gk20a *g)
unsigned int gm20b_fb_compressible_page_size(struct gk20a *g)
{
return SZ_64K;
return (unsigned int)SZ_64K;
}
u64 gm20b_fb_compression_align_mask(struct gk20a *g)

2
drivers/gpu/nvgpu/hal/fb/fb_gp10b.c
View File

@@ -34,5 +34,5 @@ u64 gp10b_fb_compression_page_size(struct gk20a *g)
unsigned int gp10b_fb_compressible_page_size(struct gk20a *g)
{
return SZ_4K;
return (unsigned int)SZ_4K;
}

16
drivers/gpu/nvgpu/hal/fb/fb_gv11b.c
View File

@@ -476,10 +476,10 @@ void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status)
/* Handle overflow */
if (corrected_overflow != 0U) {
corrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_corrected_err_count_total_s());
corrected_delta += BIT32(fb_mmu_l2tlb_ecc_corrected_err_count_total_s());
}
if (uncorrected_overflow != 0U) {
uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s());
uncorrected_delta += BIT32(fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s());
}
@@ -551,10 +551,10 @@ void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status)
/* Handle overflow */
if (corrected_overflow != 0U) {
corrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_corrected_err_count_total_s());
corrected_delta += BIT32(fb_mmu_hubtlb_ecc_corrected_err_count_total_s());
}
if (uncorrected_overflow != 0U) {
uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s());
uncorrected_delta += BIT32(fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s());
}
@@ -626,10 +626,10 @@ void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status)
/* Handle overflow */
if (corrected_overflow != 0U) {
corrected_delta += (0x1UL << fb_mmu_fillunit_ecc_corrected_err_count_total_s());
corrected_delta += BIT32(fb_mmu_fillunit_ecc_corrected_err_count_total_s());
}
if (uncorrected_overflow != 0U) {
uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s());
uncorrected_delta += BIT32(fb_mmu_fillunit_ecc_uncorrected_err_count_total_s());
}
@@ -993,7 +993,7 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g,
/* engine is faulted */
if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) {
act_eng_bitmask = BIT(mmfault->faulted_engine);
act_eng_bitmask = BIT32(mmfault->faulted_engine);
rc_type = RC_TYPE_MMU_FAULT;
}
@@ -1147,7 +1147,7 @@ static void gv11b_mm_copy_from_fault_snap_reg(struct gk20a *g,
u32 reg_val;
u32 addr_lo, addr_hi;
u64 inst_ptr;
int chid = FIFO_INVAL_CHANNEL_ID;
u32 chid = FIFO_INVAL_CHANNEL_ID;
struct channel_gk20a *refch;
(void) memset(mmfault, 0, sizeof(*mmfault));

9
drivers/gpu/nvgpu/hal/fb/fb_tu104.c
View File

@@ -29,6 +29,7 @@
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include "hal/fb/fb_gv11b.h"
#include "hal/fb/fb_gv100.h"
@@ -431,7 +432,7 @@ void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
u64 compbit_store_pa;
u64 cbc_start_addr, cbc_end_addr;
u64 cbc_top;
u32 cbc_top_size;
u64 cbc_top_size;
u32 cbc_max;
compbit_store_pa = nvgpu_mem_get_addr(g, &cbc->compbit_store.mem);
@@ -446,8 +447,9 @@ void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
fb_mmu_cbc_base_address_alignment_shift_v();
cbc_top_size = u64_lo32(cbc_top) - compbit_store_base;
nvgpu_assert(cbc_top_size < U64(U32_MAX));
nvgpu_writel(g, fb_mmu_cbc_top_r(),
fb_mmu_cbc_top_size_f(cbc_top_size));
fb_mmu_cbc_top_size_f(U32(cbc_top_size)));
cbc_max = nvgpu_readl(g, fb_mmu_cbc_max_r());
cbc_max = set_field(cbc_max,
@@ -455,8 +457,9 @@ void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
fb_mmu_cbc_max_comptagline_f(cbc->max_comptag_lines));
nvgpu_writel(g, fb_mmu_cbc_max_r(), cbc_max);
nvgpu_assert(compbit_store_base < U64(U32_MAX));
nvgpu_writel(g, fb_mmu_cbc_base_r(),
fb_mmu_cbc_base_address_f(compbit_store_base));
fb_mmu_cbc_base_address_f(U32(compbit_store_base)));
nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
"compbit base.pa: 0x%x,%08x cbc_base:0x%llx\n",