gpu: nvgpu: vgpu: create common ivc unit

Move ivc comm related functions to ivc/comm_vgpu.c.
These functions call os specific ivc counterparts.

Jira GVSCI-334

Change-Id: I886dddb71c43975cb83a3508005ab1136b7adadc
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2082183
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Aparna Das
2019-03-26 12:24:42 -07:00
committed by mobile promotions
parent 1ec9183d47
commit 012f46ef74
25 changed files with 122 additions and 46 deletions

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@@ -491,6 +491,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
common/vgpu/mm/mm_vgpu.o \
common/vgpu/mm/vm_vgpu.o \
common/vgpu/vgpu.o \
common/vgpu/ivc/comm_vgpu.o \
common/vgpu/ptimer/ptimer_vgpu.o \
common/vgpu/debugger_vgpu.o \
common/vgpu/tsg_vgpu.o \

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@@ -293,7 +293,6 @@ srcs += common/sim.c \
hal/mc/mc_gv11b.c \
hal/mc/mc_gv100.c \
hal/mc/mc_tu104.c \
common/vgpu/vgpu.c \
hal/bus/bus_gk20a.c \
hal/bus/bus_gm20b.c \
hal/bus/bus_gp10b.c \
@@ -406,6 +405,7 @@ endif
ifeq ($(IGPU_VIRT_SUPPORT), 1)
srcs += common/vgpu/vgpu.c \
common/vgpu/ivc/comm_vgpu.c \
common/vgpu/ptimer/ptimer_vgpu.c \
common/vgpu/fifo/fifo_vgpu.c \
common/vgpu/fifo/runlist_vgpu.c \

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@@ -26,6 +26,7 @@
#include <nvgpu/clk_arb.h>
#include "clk_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
static unsigned long vgpu_clk_get_rate(struct gk20a *g, u32 api_domain)
{

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@@ -31,6 +31,7 @@
#include <nvgpu/regops.h>
#include "debugger_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
int vgpu_exec_regops(struct gk20a *g,
struct channel_gk20a *ch,

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@@ -26,6 +26,7 @@
#include <nvgpu/errno.h>
#include "common/vgpu/ecc_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
int vgpu_ecc_get_info(struct gk20a *g)
{

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@@ -42,6 +42,7 @@
#include "fifo_vgpu.h"
#include "common/vgpu/gr/subctx_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>

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@@ -22,12 +22,12 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/vgpu/vgpu_ivc.h>
#include <nvgpu/vgpu/vgpu.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/channel.h>
#include "ramfc_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
int vgpu_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
u32 gpfifo_entries, u64 pbdma_acquire_timeout, u32 flags)

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@@ -32,6 +32,7 @@
#include <nvgpu/runlist.h>
#include "runlist_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
static int vgpu_submit_runlist(struct gk20a *g, u64 handle, u8 runlist_id,
u16 *runlist, u32 num_entries)

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@@ -29,6 +29,7 @@
#include "gv11b/fifo_gv11b.h"
#include "common/vgpu/fifo/vgpu_fifo_gv11b.h"
#include "common/vgpu/ivc/comm_vgpu.h"
#ifdef CONFIG_TEGRA_GK20A_NVHOST

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@@ -33,6 +33,7 @@
#include <nvgpu/gr/ctx.h>
#include "ctx_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx,

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@@ -31,7 +31,7 @@
#include <nvgpu/gk20a.h>
#include "fecs_trace_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
int vgpu_fecs_trace_init(struct gk20a *g)
{

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@@ -50,6 +50,8 @@
#include "subctx_vgpu.h"
#include "common/vgpu/perf/cyclestats_snapshot_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
#include "common/gr/zcull_priv.h"
static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g,

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@@ -26,6 +26,7 @@
#include <nvgpu/gr/subctx.h>
#include "subctx_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
int vgpu_alloc_subctx_header(struct gk20a *g,
struct nvgpu_gr_subctx **gr_subctx,

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@@ -26,6 +26,7 @@
#include <nvgpu/channel.h>
#include "vgpu_tsg_gv11b.h"
#include "common/vgpu/ivc/comm_vgpu.h"
int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
struct channel_gk20a *ch)

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@@ -0,0 +1,63 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/bug.h>
#include <nvgpu/string.h>
#include <nvgpu/vgpu/vgpu_ivc.h>
#include <nvgpu/vgpu/tegra_vgpu.h>
#include "comm_vgpu.h"
int vgpu_comm_init(struct gk20a *g)
{
size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
return vgpu_ivc_init(g, 3, queue_sizes, TEGRA_VGPU_QUEUE_CMD,
ARRAY_SIZE(queue_sizes));
}
void vgpu_comm_deinit(void)
{
size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
vgpu_ivc_deinit(TEGRA_VGPU_QUEUE_CMD, ARRAY_SIZE(queue_sizes));
}
int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
size_t size_out)
{
void *handle;
size_t size = size_in;
void *data = msg;
int err;
err = vgpu_ivc_sendrecv(vgpu_ivc_get_server_vmid(),
TEGRA_VGPU_QUEUE_CMD, &handle, &data, &size);
if (err == 0) {
WARN_ON(size < size_out);
nvgpu_memcpy((u8 *)msg, (u8 *)data, size_out);
vgpu_ivc_release(handle);
}
return err;
}

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@@ -0,0 +1,34 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef COMM_VGPU_H
#define COMM_VGPU_H
struct gk20a;
struct tegra_vgpu_cmd_msg;
int vgpu_comm_init(struct gk20a *g);
void vgpu_comm_deinit(void);
int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
size_t size_out);
#endif

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@@ -35,6 +35,7 @@
#include "mm_vgpu.h"
#include "gk20a/mm_gk20a.h"
#include "gm20b/mm_gm20b.h"
#include "common/vgpu/ivc/comm_vgpu.h"
static int vgpu_init_mm_setup_sw(struct gk20a *g)
{

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@@ -27,14 +27,14 @@
#include <nvgpu/bug.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/channel.h>
#include <nvgpu/vgpu/vgpu.h>
#include <nvgpu/vm.h>
#include <nvgpu/vm_area.h>
#include <nvgpu/vgpu/vgpu.h>
#include <nvgpu/vgpu/vm_vgpu.h>
#include "common/vgpu/ivc/comm_vgpu.h"
/*
* This is called by the common VM init routine to handle vGPU specifics of
* intializing a VM on a vGPU. This alone is not enough to init a VM. See

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@@ -31,6 +31,7 @@
#include <nvgpu/cyclestats_snapshot.h>
#include "cyclestats_snapshot_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
static struct tegra_hv_ivm_cookie *css_cookie;

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@@ -26,6 +26,7 @@
#include <nvgpu/gk20a.h>
#include "perf_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
static int vgpu_sendrecv_perfbuf_cmd(struct gk20a *g, u64 offset, u32 size)
{

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@@ -29,6 +29,7 @@
#include <nvgpu/vgpu/vgpu.h>
#include "fifo/fifo_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
int vgpu_tsg_open(struct tsg_gk20a *tsg)
{

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@@ -34,40 +34,7 @@
#include <nvgpu/cbc.h>
#include "common/vgpu/gr/fecs_trace_vgpu.h"
int vgpu_comm_init(struct gk20a *g)
{
size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
return vgpu_ivc_init(g, 3, queue_sizes, TEGRA_VGPU_QUEUE_CMD,
ARRAY_SIZE(queue_sizes));
}
void vgpu_comm_deinit(void)
{
size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
vgpu_ivc_deinit(TEGRA_VGPU_QUEUE_CMD, ARRAY_SIZE(queue_sizes));
}
int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
size_t size_out)
{
void *handle;
size_t size = size_in;
void *data = msg;
int err;
err = vgpu_ivc_sendrecv(vgpu_ivc_get_server_vmid(),
TEGRA_VGPU_QUEUE_CMD, &handle, &data, &size);
if (!err) {
WARN_ON(size < size_out);
nvgpu_memcpy((u8 *)msg, (u8 *)data, size_out);
vgpu_ivc_release(handle);
}
return err;
}
#include "common/vgpu/ivc/comm_vgpu.h"
u64 vgpu_connect(void)
{

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@@ -32,7 +32,6 @@
struct device;
struct tegra_vgpu_gr_intr_info;
struct tegra_vgpu_fifo_intr_info;
struct tegra_vgpu_cmd_msg;
struct nvgpu_mem;
struct gk20a;
struct vm_gk20a;
@@ -64,11 +63,6 @@ static inline u64 vgpu_get_handle(struct gk20a *g)
return priv->virt_handle;
}
int vgpu_comm_init(struct gk20a *g);
void vgpu_comm_deinit(void);
int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
size_t size_out);
u64 vgpu_connect(void);
int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
int vgpu_intr_thread(void *dev_id);
void vgpu_remove_support_common(struct gk20a *g);

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@@ -20,6 +20,7 @@
#include "os/linux/platform_gk20a.h"
#include "os/linux/os_linux.h"
#include "common/vgpu/ecc_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
static ssize_t vgpu_load_show(struct device *dev,
struct device_attribute *attr,

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@@ -38,6 +38,7 @@
#include "vgpu_linux.h"
#include "common/vgpu/gr/fecs_trace_vgpu.h"
#include "common/vgpu/clk_vgpu.h"
#include "common/vgpu/ivc/comm_vgpu.h"
#include "gm20b/hal_gm20b.h"
#include "os/linux/module.h"