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git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
gpu: nvgpu: vgpu: create common ivc unit
Move ivc comm related functions to ivc/comm_vgpu.c. These functions call os specific ivc counterparts. Jira GVSCI-334 Change-Id: I886dddb71c43975cb83a3508005ab1136b7adadc Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2082183 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -491,6 +491,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
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common/vgpu/mm/mm_vgpu.o \
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common/vgpu/mm/vm_vgpu.o \
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common/vgpu/vgpu.o \
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common/vgpu/ivc/comm_vgpu.o \
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common/vgpu/ptimer/ptimer_vgpu.o \
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common/vgpu/debugger_vgpu.o \
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common/vgpu/tsg_vgpu.o \
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@@ -293,7 +293,6 @@ srcs += common/sim.c \
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hal/mc/mc_gv11b.c \
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hal/mc/mc_gv100.c \
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hal/mc/mc_tu104.c \
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common/vgpu/vgpu.c \
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hal/bus/bus_gk20a.c \
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hal/bus/bus_gm20b.c \
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hal/bus/bus_gp10b.c \
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@@ -406,6 +405,7 @@ endif
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ifeq ($(IGPU_VIRT_SUPPORT), 1)
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srcs += common/vgpu/vgpu.c \
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common/vgpu/ivc/comm_vgpu.c \
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common/vgpu/ptimer/ptimer_vgpu.c \
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common/vgpu/fifo/fifo_vgpu.c \
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common/vgpu/fifo/runlist_vgpu.c \
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@@ -26,6 +26,7 @@
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#include <nvgpu/clk_arb.h>
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#include "clk_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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static unsigned long vgpu_clk_get_rate(struct gk20a *g, u32 api_domain)
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{
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@@ -31,6 +31,7 @@
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#include <nvgpu/regops.h>
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#include "debugger_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_exec_regops(struct gk20a *g,
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struct channel_gk20a *ch,
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@@ -26,6 +26,7 @@
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#include <nvgpu/errno.h>
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#include "common/vgpu/ecc_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_ecc_get_info(struct gk20a *g)
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{
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@@ -42,6 +42,7 @@
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#include "fifo_vgpu.h"
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#include "common/vgpu/gr/subctx_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
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@@ -22,12 +22,12 @@
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include "ramfc_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
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u32 gpfifo_entries, u64 pbdma_acquire_timeout, u32 flags)
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@@ -32,6 +32,7 @@
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#include <nvgpu/runlist.h>
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#include "runlist_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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static int vgpu_submit_runlist(struct gk20a *g, u64 handle, u8 runlist_id,
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u16 *runlist, u32 num_entries)
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@@ -29,6 +29,7 @@
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#include "gv11b/fifo_gv11b.h"
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#include "common/vgpu/fifo/vgpu_fifo_gv11b.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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#ifdef CONFIG_TEGRA_GK20A_NVHOST
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@@ -33,6 +33,7 @@
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#include <nvgpu/gr/ctx.h>
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#include "ctx_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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@@ -31,7 +31,7 @@
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#include <nvgpu/gk20a.h>
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#include "fecs_trace_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_fecs_trace_init(struct gk20a *g)
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{
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@@ -50,6 +50,8 @@
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#include "subctx_vgpu.h"
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#include "common/vgpu/perf/cyclestats_snapshot_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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#include "common/gr/zcull_priv.h"
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static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g,
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@@ -26,6 +26,7 @@
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#include <nvgpu/gr/subctx.h>
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#include "subctx_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_alloc_subctx_header(struct gk20a *g,
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struct nvgpu_gr_subctx **gr_subctx,
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@@ -26,6 +26,7 @@
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#include <nvgpu/channel.h>
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#include "vgpu_tsg_gv11b.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
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struct channel_gk20a *ch)
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63
drivers/gpu/nvgpu/common/vgpu/ivc/comm_vgpu.c
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63
drivers/gpu/nvgpu/common/vgpu/ivc/comm_vgpu.c
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@@ -0,0 +1,63 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/string.h>
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include <nvgpu/vgpu/tegra_vgpu.h>
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#include "comm_vgpu.h"
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int vgpu_comm_init(struct gk20a *g)
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{
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size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
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return vgpu_ivc_init(g, 3, queue_sizes, TEGRA_VGPU_QUEUE_CMD,
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ARRAY_SIZE(queue_sizes));
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}
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void vgpu_comm_deinit(void)
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{
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size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
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vgpu_ivc_deinit(TEGRA_VGPU_QUEUE_CMD, ARRAY_SIZE(queue_sizes));
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}
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int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
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size_t size_out)
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{
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void *handle;
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size_t size = size_in;
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void *data = msg;
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int err;
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err = vgpu_ivc_sendrecv(vgpu_ivc_get_server_vmid(),
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TEGRA_VGPU_QUEUE_CMD, &handle, &data, &size);
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if (err == 0) {
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WARN_ON(size < size_out);
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nvgpu_memcpy((u8 *)msg, (u8 *)data, size_out);
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vgpu_ivc_release(handle);
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}
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return err;
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}
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34
drivers/gpu/nvgpu/common/vgpu/ivc/comm_vgpu.h
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34
drivers/gpu/nvgpu/common/vgpu/ivc/comm_vgpu.h
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@@ -0,0 +1,34 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef COMM_VGPU_H
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#define COMM_VGPU_H
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struct gk20a;
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struct tegra_vgpu_cmd_msg;
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int vgpu_comm_init(struct gk20a *g);
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void vgpu_comm_deinit(void);
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int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
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size_t size_out);
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#endif
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@@ -35,6 +35,7 @@
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#include "mm_vgpu.h"
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#include "gk20a/mm_gk20a.h"
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#include "gm20b/mm_gm20b.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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static int vgpu_init_mm_setup_sw(struct gk20a *g)
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{
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@@ -27,14 +27,14 @@
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#include <nvgpu/bug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/vm.h>
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#include <nvgpu/vm_area.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/vgpu/vm_vgpu.h>
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#include "common/vgpu/ivc/comm_vgpu.h"
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/*
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* This is called by the common VM init routine to handle vGPU specifics of
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* intializing a VM on a vGPU. This alone is not enough to init a VM. See
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@@ -31,6 +31,7 @@
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#include <nvgpu/cyclestats_snapshot.h>
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#include "cyclestats_snapshot_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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static struct tegra_hv_ivm_cookie *css_cookie;
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@@ -26,6 +26,7 @@
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#include <nvgpu/gk20a.h>
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#include "perf_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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static int vgpu_sendrecv_perfbuf_cmd(struct gk20a *g, u64 offset, u32 size)
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{
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@@ -29,6 +29,7 @@
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#include <nvgpu/vgpu/vgpu.h>
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#include "fifo/fifo_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_tsg_open(struct tsg_gk20a *tsg)
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{
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@@ -34,40 +34,7 @@
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#include <nvgpu/cbc.h>
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#include "common/vgpu/gr/fecs_trace_vgpu.h"
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int vgpu_comm_init(struct gk20a *g)
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{
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size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
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return vgpu_ivc_init(g, 3, queue_sizes, TEGRA_VGPU_QUEUE_CMD,
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ARRAY_SIZE(queue_sizes));
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}
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void vgpu_comm_deinit(void)
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{
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size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
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vgpu_ivc_deinit(TEGRA_VGPU_QUEUE_CMD, ARRAY_SIZE(queue_sizes));
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}
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int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
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size_t size_out)
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{
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void *handle;
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size_t size = size_in;
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void *data = msg;
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int err;
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err = vgpu_ivc_sendrecv(vgpu_ivc_get_server_vmid(),
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TEGRA_VGPU_QUEUE_CMD, &handle, &data, &size);
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if (!err) {
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WARN_ON(size < size_out);
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nvgpu_memcpy((u8 *)msg, (u8 *)data, size_out);
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vgpu_ivc_release(handle);
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}
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return err;
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}
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#include "common/vgpu/ivc/comm_vgpu.h"
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u64 vgpu_connect(void)
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{
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@@ -32,7 +32,6 @@
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struct device;
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struct tegra_vgpu_gr_intr_info;
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struct tegra_vgpu_fifo_intr_info;
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struct tegra_vgpu_cmd_msg;
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struct nvgpu_mem;
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struct gk20a;
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struct vm_gk20a;
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@@ -64,11 +63,6 @@ static inline u64 vgpu_get_handle(struct gk20a *g)
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return priv->virt_handle;
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}
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int vgpu_comm_init(struct gk20a *g);
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void vgpu_comm_deinit(void);
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int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
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size_t size_out);
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u64 vgpu_connect(void);
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int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
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int vgpu_intr_thread(void *dev_id);
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void vgpu_remove_support_common(struct gk20a *g);
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@@ -20,6 +20,7 @@
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#include "os/linux/platform_gk20a.h"
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#include "os/linux/os_linux.h"
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#include "common/vgpu/ecc_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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static ssize_t vgpu_load_show(struct device *dev,
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struct device_attribute *attr,
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@@ -38,6 +38,7 @@
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#include "vgpu_linux.h"
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#include "common/vgpu/gr/fecs_trace_vgpu.h"
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#include "common/vgpu/clk_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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#include "gm20b/hal_gm20b.h"
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#include "os/linux/module.h"
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